SoC RTL Design Developer

Requirements:

• Experience in Logic design /micro-architecture / RTL coding is a must.
• Must have hands-on experience with SoC design and integration for SoCs.
• Experience in Verilog/System-Verilog is a must.
• Should know AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIe, and SDCC.
• Understanding of Memory controller designs and microprocessors is an added advantage.
• Hands-on experience in constraint development and timing closure.
• Work closely with the SoC verification and validation teams for pre/post Silicon debug.
• Hands-on experience in low-power SoC design is required.
• Experience in Synthesis / Understanding of timing concepts for ASIC is required.
• Hands-on experience in multi-clock designs Asynchronous interface is a must.
• Experience creating pad ring and working with the chip-level floorplan team is an added advantage.
• Experience in using the tools in ASIC development such as Lint, CDC, Design Compiler, and PrimeTime is required.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• 8+ years of experience in digital front-end ASIC/RTL design.

Skills

ahb, amba, apb, asic, axi, rtl, soc, system verilog, systemverilog, verilog