Sr Staff Engineer, Power Delivery

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Job Area:

General Summary:

As a Qualcomm Hardware Engineer specializing in On-Chip Power Delivery Network (PDN) Architecture, you will define, develop, and optimize power-grid architectures for advanced-node, high-performance SoCs.

This role focuses on on-die power delivery and power-grid (PG) architecture, including power-grid topology, rail structure, PDN-aware floorplanning, on-die decoupling, bump connectivity, IR drop, dynamic voltage droop, electromigration (EM), coupling, and advanced power-delivery technologies.

You will work closely with SoC Architecture, Physical Design, IP Design, Package/PI, and technology teams to develop scalable PDN solutions that meet demanding performance, power, area (PPA), reliability, and routing requirements across advanced technology nodes.

Responsibilities

• Own on-chip power delivery network architecture and power-grid strategy for advanced-node, high-performance SoCs.
• Define and optimize power-grid topology, rail structure, power domains, grid architecture, and power/ground distribution for high-current CPU, NSP, GPU, and other performance-critical IPs.
• Drive PDN-aware floorplanning in collaboration with SoC Physical Design and IP teams to optimize power delivery while considering PPA, routing resources, timing, and implementation constraints.
• Define and optimize on-die power-grid connectivity to bump interfaces, including bump allocation and interaction between the on-die PG, package PDN, and decoupling capacitance.
• Define and optimize the on-die decoupling-capacitance strategy, including decap allocation, placement, and effectiveness across the applicable PDN frequency range.
• Establish static IR-drop, dynamic voltage-droop, impedance, EM/current-density, and reliability budgets for performance-critical power rails.
• Perform and drive static IR, dynamic voltage-drop, transient, impedance, EM, and PDN coupling analyses to achieve power-integrity closure.
• Co-optimize the on-chip power grid with floorplan, timing, PPA, routing resources, bump allocation, and package connectivity, particularly for advanced nodes with increasingly constrained routing resources.
• Define the on-chip PG roadmap for advanced technology nodes, including evaluation and tradeoff analysis of conventional front-side power grids, backside power delivery, and other emerging power-delivery technologies.
• Drive PGPOR roadmap and architecture tradeoff analysis, including power-grid architecture, rail structure, implementation options, and advanced PDN solutions.
• Partner closely with Physical Design, SoC Architecture, IP Design, Package/PI, and technology teams from early architecture and floorplanning through implementation and design closure.
• Develop scalable PDN extraction, modeling, simulation, signoff, and correlation methodologies to support advanced-node SoC development.

Preferred Qualifications

• Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, or related field with a focus on power integrity, VLSI, physical design, or semiconductor power delivery.
• Deep expertise in on-chip power-grid architecture, PDN optimization, and advanced-node power delivery.
• Experience with Cadence Voltus, Sigrity PowerSI, Ansys HFSS/Q3D/SiWave, HSpice, ADS, or equivalent power-integrity and circuit-simulation tools.
• Experience developing or improving PDN extraction, modeling, analysis, automation, and signoff methodologies.
• Knowledge of advanced power-grid technologies, backside power delivery, advanced packaging, and die-to-package power-delivery co-optimization.
• Strong scripting and automation skills using Python, TCL, or similar languages.
• Demonstrated ability to work cross-functionally with SoC Architecture, Physical Design, IP, Package, PI, and technology teams.

Minimum Qualifications:

OR

Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of System/Package Design/Technology Engineering or related work experience.

OR

PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ year of System/Package Design/Technology Engineering or related work experience.

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Pay rangeand Other Compensation & Benefits :

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.