SystemC Modeling Engineer

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General Summary:

Looking for SystemC Modeling Engineers to build models for Turing AI accelerator subsystems, including compression engines and data movement architectures.

Strong C++/SystemC expertise with experience in performance modeling and HW/SW co-design.

Collaborate with architecture, design, firmware, and DV teams to drive early feature validation and performance optimization.

A strong foundation in Digital Design, RTL, and functional Verification concepts is a must. The candidate should understand how RTL micro-architecture maps to behavioral models and be able to reason about pipelines, locking/timing, and functional correctness to ensure the SystemC models faithfully represent the intended hardware.

Experience with memory hierarchies and transaction-level modeling (TLM) is a plus.

Minimum Qualifications:

OR

Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

OR

PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.

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