Senior Advanced Semiconductor Packaging Engineer - 1119

We are seeking a Senior Advanced Semiconductor Packaging Engineer to work either at one of our Minneapolis, MN sites or at a supplier site in Malta, NY as a full-time Quantinuum employee to develop innovative and reliable packaging schemes for the highly-scaled ion traps in our quantum computers. The ideal candidate will be a mid-career engineer with a background in advanced packaging concepts. This role will work alongside ASIC designers, ion trap designers and fabricators, optical designers, and third-party vendors to prototype, design, and fabricate ion trap assemblies for our quantum computers. Candidates should expect to be immersed in a fast-paced, multi-functional, team-based challenging technical environment where an individual with talent and initiative can stand out and thrive.

All applicants for placement in safety-sensitive positions will be required to submit to a pre-employment drug test.

Key Responsibilities:

• Develop and implement advanced packaging concepts for mechanical, thermal, electrical, optical, and detection interfaces to next-generation ion traps
• Develop packaging strategies and processes for large-format ion trap chips with high I/O signal count and density
• Work with vendors to implement and validate packaging processes
• Support all stages of ion trap development to ensure compatibility with packaging
• Interface with broader Quantinuum team to ensure ion trap packaging meets system requirements
• Engage with 3rd parties to cultivate possible key partnerships, supplier relationships, and co-development opportunities

YOU MUST HAVE:

• Bachelor’s degree minimum
• 5+ years of experience in an engineering or R&D environment
• 3+ years of experience in advanced semiconductor packaging development
• Due to Contractual requirements, must be a U.S. Person. defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status

WE VALUE:

• PhD in Physics or Engineering
• 7 years of experience with advanced large-area multi-chip semiconductor packaging technologies
• 5 years of experience with large heterogeneous integration and 2.5-3D packaging techniques
• 5 years of experience with high-density I/O technologies
• Experience with photonic packaging and fiber-to-chip coupling is a plus
• A proven track record of innovation and IP development
• Experience working within a cross-functional team environment