412,983open jobs
14,312companies
71,936added this week
Browse all
Salary
$134k – $249k per year
Location
In office
Seniority
Staff · 10+ years exp
Overview
Company
Impact
Profile match
Dedicated to making data faster and safer, Rambus creates innovative hardware and services that drive technology advancements to data centers, IoT, AI & more!

Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU’s engineering team in John's Creek, Georgia. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s.

Responsibilities

  • Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio
  • Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis
  • Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores
  • Work with our customers to do collaboration to find the optimum SI/PI solution
  • Help the team during debug and bring up in lab if needed

Qualifications

  • Solid background in SI/PI and package design to provide technical leadership to the team
  • Strong interpersonal skill to keep the team motivated and focused
  • MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5
  • Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required
  • Solid theoretical background and understanding in EM and transmission line theory is a must
  • Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required
  • Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system
  • Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc.
  • Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable
  • Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
  • Proficient with simulations using Spice and ADS
  • Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
  • Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
  • Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus
  • Basic knowledge of circuits used in high-speed link design is preferred.
  • Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams.
  • Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player

About Rambus

With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US- John's Creek, GA salary range for this full-time position is $133,900 to $248,700. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.

For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

#LIF-GL

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
412,983 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Similar stack
Same company
In your city
In office • 14+ years exp • Bachelor's Degree
Python
Chips/EDA
Cadence Allegro
OrCAD
Apply
$135k – $183k per year • Equity • In office • 7+ years exp • Bachelor's Degree • Carlsbad
Chips/EDA
Ansys HFSS
Cadence Allegro
Cadence Sigrity
Ansys SIwave
Apply
$158k – $193k per year • Equity • In office • 9+ years exp • Bachelor's Degree • Carlsbad
Chips/EDA
Ansys HFSS
Cadence Allegro
Cadence Sigrity
Ansys SIwave
Apply
$100k – $137k per year • Equity • In office • Full-Time • 3+ years exp • Master's Degree • Santa Clara
Chips/EDA
Cadence Allegro
OrCAD
Apply
$102k – $198k per year (Estimated) • In office • Top Secret • Full-Time • 6+ years exp • Bachelor's Degree • United States
Python
C++
VHDL
MATLAB
DevOps
RTOS
Chips/EDA
KiCad
Siemens ModelSim
Xilinx Vivado
Active-HDL
Libero SoC
Lattice Diamond
Cadence Allegro
OrCAD
Vitis
IoT
FreeRTOS
Apply
$107k – $199k per year • Remote/Hybrid • 5+ years exp • Hillsboro
Python
Verilog
SystemVerilog
Perl
TCL Scripting
Apply
$108k – $200k per year • Remote/Hybrid • 5+ years exp
Apply
$58k – $108k per year • Equity • Remote/Hybrid • 2+ years exp • Bachelor's Degree
Python
Verilog
SystemVerilog
Apply
$31k – $73k per year (Estimated) • Remote/Hybrid • 6+ years exp • Master's Degree • Sofia
Python
Verilog
SystemVerilog
Chips/EDA
UVM
Apply
$158k per year • Remote/Hybrid • 12+ years exp • Bachelor's Degree
Python
Perl
Apply
See all jobs
This is one of many
412,983 more open roles from verified company boards, updated every day.