SoC/Subsystem Design Engineer

About the Job

As a Senior SoC/Subsystem Design Engineer, you will lead the architecture and integration of next-generation AI acceleration systems. This role demands a high-level integration of RTL design expertise and system-level optimization to ensure robust performance and power under dynamic workloads. You will drive cross-functional collaboration to deliver high-reliability silicon from initial architecture to final bring-up.

Responsibilities and Opportunities

• AI Architecture & Integration: Lead the architectural definition of SoC or Subsystem, RTL design, and system integration for high-performance AI acceleration SoCs
• Cross-Functional Collaboration: Partner closely with verification, software, and backend teams to ensure seamless IP integration and full-stack system functionality
• DSP & Logic Implementation: Collaborate with DSP engineers to bridge the gap between complex algorithms and hardware implementation
• Silicon Bring-up & Validation: Drive the silicon bring-up process, leading hardware/software debugging to ensure mission-critical reliability
• Innovative System Design: Opportunity to apply advanced clock and power control design and methodologies to enhance SoC robustness and immunity against environmental perturbations

Key Qualifications

• 10+ years of experience in high-complexity RTL design using SystemVerilog or Verilog
• Subsystem Leadership: Proven track record of leading SoC subsystem designs from conceptual architecture to physical implementation
• Advanced Toolchain Proficiency: * Simulation: Expert in VCS or Xcelium for debugging complex RTL issues and Gate Level Simulation issue
• Quality & Integration: Mastery of Lint, CDC, RDC, DFT, and Synthesis flows, along with automated integration tools like IP-XACT
• End-to-End Design Experience: Comprehensive understanding of the full SoC lifecycle, including power-on reset sequences and clock domain crossing

Ideal Qualifications

• Infrastructure Design: Deep experience in designing and optimizing Clock, Reset, and Power Control Units
• Memory Management: Understanding of ARM MMU architectures and memory coherency protocols

전형절차

• 서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit 인터뷰 > 처우 협의 > 최종 합격
• 전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.
• 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.

참고사항

• 본 공고는 모집 완료 시 조기 마감될 수 있습니다.
• 지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.
• 채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.
• 보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.
• 담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.
• 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다.
• [email protected]