RTL Engineer

About the Job

Rebellions is the first company in the world to productize a UCIe-based die-to-die (D2D) interconnect for AI accelerator, stitching multiple NPU dies into a single chiplet system. As a RTL Engineer, you will own the RTL of the blocks that move data between dies - the communication backbone of the chiplet system. You will work side-by-side with the interconnect architect to concretize the microarchitecture of our next-generation D2D interconnect and carry it from spec to working silicon.

Your immediate focus is D2D. Over time, the same interconnect RTL skills open the door to other high-speed interconnects across the HSIO roadmap at Rebellions. You do not need prior UCIe or D2D experience - we point strong interconnect RTL engineers at the standard and ramp them here.

Adjacent experience counts. If you have built RTL for PCIe or CXL controllers, Ethernet MAC/PCS, memory controllers, NoC or AMBA fabrics, or any packetized link layer, that maps directly onto this role.

Responsibilities and Opportunities

• Interconnect RTL Design: design and implement the D2D interconnect subsystem - transaction management and datapath, link-level reliability (retry/replay, CRC, FEC), and built-in test, debug, and monitoring structures (traffic generation/comparison, loopback, per-port counters, performance monitors).
• NPU SoC System View: work with a system-level view of the NPU SoC. The D2D subsystem carries accelerator traffic, so its microarchitecture follows from how compute, memory hierarchy, and NoC move data. You will build that view here, alongside the architect.
• Microarchitecture Definition: concretize the interconnect microarchitecture together with the architect - including the areas that industry specs leave under-defined.
• Standard-Spec-Based Design: design against open standards (UCIe, CHI, CHI C2C and related specs) and integrate vendor controller/PHY IP through standard interfaces (e.g., RDI/FDI/AXI) and Rebellions in-house NoC interface.
• Cross-Functional Collaboration: partner with verification, SoC integration, firmware (register map / control interface), and PSI teams to make the subsystem work in the real system.
• Silicon Bring-up: participate in D2D link bring-up and support post-silicon debugging down to RTL simulation when issues go deep.

Key Qualifications

• Minimum 6+ years of combined experience in RTL design using SystemVerilog/Verilog (M.S. counted as 2 years, Ph.D. as 4 years toward this total). Fewer years with clear depth in interconnect or link-layer RTL is also worth a conversation.
• Block Ownership: you have owned at least one non-trivial block end to end in RTL. Prior architecture-definition experience is welcome but not required - you will define microarchitecture here with the architect beside you, not alone.
• Simulation & Debugging: proficiency in a logic simulation tool (VCS or Xcelium) with the ability to root-cause complex RTL issues.
• Quality Toolchain: familiarity with industry-standard quality flows - Lint, CDC, and Synthesis at minimum.
• Communication & collaboration:. strong, collaborative cross-functional work - root-causing a chiplet issue spans architecture, verification, firmware, PSI, and vendor teams, so we value engineers who debug with data rather than blame and own their mistakes honestly.

Preferred Qualifications

• Tape-out & Silicon Bring-up: experience carrying a design through tape-out and into post-silicon debug. Valuable here, but not a requirement - the role includes bring-up, so you can also learn it on this project.
• Interconnect Protocols: working knowledge of AMBA (AXI/ACE) or CHI, or any packetized on-chip protocol - transaction ordering, outstanding-transaction management, and credit-based flow control.
• Clock, Reset & Low-Power Infrastructure: clock domain crossing, reset domain crossing, and power/clock gating in a multi-domain design.
• DFT: scan insertion, compression, and DFT-aware RTL practices.
• SerDes / high-speed PHY: working understanding of SerDes-based high-speed links - PCS/PMA partitioning, equalization, clock/data recovery, and link training - and the digital logic that interfaces to a SerDes PHY.

Growth Path

• D2D architecture, from spec to silicon: you will work daily with the interconnect architect on next-generation D2D architecture, and experience standard-spec-based design at a company that actually ships it - from an evolving industry spec all the way to productized silicon.
• Beyond D2D: as the HSIO roadmap expands, you can grow into RTL design for other high-speed IO domains - Ethernet, optical interconnect, and whatever comes next.

Note: this role centers on interconnect and communication IP. If you enjoy making dies talk to each other reliably at high speed - rather than building the compute die itself - this is the seat. Prior high-speed IO IP design experience is not required: solid IP design experience in another domain is a strong basis to apply.

전형절차

• 서류전형 > On-line 인터뷰 > On-site 인터뷰 > Culture-fit인터뷰 > 처우 협의 > 최종 합격
• 전형절차는 직무별로 다르게 운영될 수 있으며, 일정 및 상황에 따라 변동될 수 있습니다.
• 전형 일정 및 결과는 지원 시 작성하신 이메일로 개별 안내드립니다.

참고사항

• 본 공고는 모집 완료 시 조기 마감될 수 있습니다.
• 지원서 내용 중 허위사실이 있는 경우에는 합격이 취소될 수 있습니다.
• 채용 및 업무 수행과 관련하여 요구되는 법령 상 자격이 갖추어지지 않은 경우 채용이 제한될 수 있습니다.
• 보훈 대상자 및 장애인 여부는 채용 과정에서 어떠한 불이익도 미치지 않습니다.
• 담당 업무 범위는 후보자의 전반적인 경력과 경험 등 제반사정을 고려하여 변경될 수 있습니다. 이러한 변경이 필요할 경우, 최종 합격 통지 전 적절한 시기에 후보자와 커뮤니케이션 될 예정입니다.
• 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다.
• [email protected]