Physical Designer Engineer, Synthesis/PnR

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Role Summary

As a Physical Design Engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block and subchip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to drive the overall Physical Design aspects, leading to a successful tapeout and production silicon.

Responsibilities

• Perform subchip level and block level place and route, and close design to meeting performance, power and area.
• Lead and perform all aspects of full chip SoC integration activities: die size optimization, floorplanning, hard IP integration, partitioning, block/chip level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing, DFT strategy planning, and final physical verification.
• Good knowledge of timing analysis, power analysis, physical verification (DRC/LVS), and formal verification
• Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation.
• Define EM-IR signoff requirements and sign-off methodology.
• Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis
• Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on- die model for package & die co-design analysis
• Be an EM-IR sign-off lead with successful tape out track records
• Excellent hand-on experience in voltage drop analysis using redhawk or redhawk-SC
• Excellent hand-on experience and debugging skills of finding root cause of voltage drop and EM issues
• Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to detail
• Work closely with the Foundry Engineer and Microarchitecture team to establish logic levels, Multi-Vt library mixes and choices of tracks, metal-stackup, etc.
• Define flows through various EDA tools and write scripts for automation for floor planning, placement, routing, crosstalk avoidance, judicious usage of cell libraries and physical verification
• Work with the Microarchitecture, Signal Integrity, Power Integrity and Thermal team to ensure that the floorplan and the logic is designed in such a way such that the Substrate/Packaging and Board Layout and the Power Delivery comprehend the power domains, multiple voltages, power integrity requirements, power gating, specify power sequencing to eliminate leakage paths, always-on power, minimize hot-spots, etc.
• Design the floorplan to ensure that the power distribution for the chip for the various voltage domains is consistent with the bump and bump-ball map to ensure power integrity (i.e., minimize voltage droop, utilization of local LDOs) and signal integrity (e.g., aggressor nets)
• Ensure that the clocking architecture is robust and meets the timing requirements - i.e., well versed in Clock Tree Synthesis, Static Timing Analysis, Timing closure methodologies, Clock gating, reference clocks, PLL placement, clock muxing, etc.
• Well versed in parasitic extraction, LVS/DRC and other verification checks - Physical, Power, Post-Layout Timing

Qualifications

• At least 12 years of experience in the chip industry with a track record of delivering silicon into volume production across multiple technology generations
• Proven track record of SoC definition of complex SoCs over multiple technology generations
• BS/MS/PhD in Electrical and Computer Engineering with emphasis on Computer Architecture
• Experienced in CPU Architecture - preferably Instruction Decode or Execution Units
• Experience in Multi SoC systems is a plus
• Knowledge of Machine Learning Algorithms (e.g., Convolutional Neural Networks) is a huge plus
• Exhibits the right teamwork and leadership qualities backed up with references
• Extensive physical design experiences at both the block level and subchip level, as well as full-chip level is a plus.
• Deep knowledge in physical design, including physical aware synthesis, floorplanning, clock tree implementation, routing, STA timing signoff, and chip-finishing.
• Solid experience in advanced process nodes (e.g. 5nm and below) and associated DRC/DFM challenges
• Experience with MSCTS or custom H-tree clock implementation
• Good knowledge of basic soc architecture. Be able to work with Front-end design team to address timing, congestion and power issues.
• In-Depth Knowledge of design flow from RTL to GDSII.
• Solid understanding of STA, SDC, MCMM and on-chip variation
• Good knowledge of EM-IR sign-off requirements.
• Experience in using EDA tools like Synopsys (/Cadence) for PPA optimization.
• Good script skills such as python/tcl.
• Good communication skills: documentation skills and cross-functional skills.

Pay Disclosure

The listed base salary range for this role is $186,00 - $232,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.

Equal Opportunity

Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law.

Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at [email protected].

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How We Use AI in Our Hiring Process: To ensure transparency, we want candidates to know that Rivian uses iCIMS Talent Cloud Artificial Intelligence (TCAI) and AI-enabled tools to assist with screening, reviewing, organizing and highlighting profiles and applications that match the key requirements for each role.

AI does not make hiring decisions: Qualified candidate applications are reviewed by a member of our team, and all decisions throughout the process are made by humans. We use AI to support efficiency and consistency, not to replace human judgment. We are committed to a fair, thoughtful, and equitable experience for every candidate.

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