Director- R&D Technical Head
Confirmed on the employer's own hiring board on Oct 5, 2026. First seen by Alion on Aug 6, 2026. Semtech scores B on the Alion truth index.
RESPONSIBILITIES
Technical Leadership & Strategy (40%)
Define and own the end-to-end chip design strategy, methodology, and technology roadmap across all design verticals - SoC, Analog, Digital, Product & Test Engineering, Design Packaging, Verification and DFT.
Establish design standards, best practices, and quality benchmarks to ensure silicon correctness, power-performance-area (PPA) targets, and first-silicon success rates.
Evaluate and adopt state-of-the-art EDA toolchains (Cadence, Synopsys, Siemens EDA) and emerging design methodologies to maintain competitive advantage.
Provide architectural guidance on SoC partitioning, IP integration, mixed-signal co-design, and design-for-manufacturability (DFM) across advanced process nodes.
Team Management & People Leadership (30%)
Directly manage all vertical leads and engineering managers SoC, Analog, Digital, Product & Test Engineering, Design Packaging, Verification and DFT.
Set clear goals, conduct regular reviews, and create individual development plans to build a high-performing, future-ready engineering organization.
Drive talent acquisition strategy in partnership with HR; define technical interview frameworks and competency benchmarks for senior engineering hires.
Foster a culture of technical excellence, collaboration, and continuous learning across a team of 12-20+ direct and indirect reports.
Project Monitoring & Cross-Vertical Coordination (15%)
Engage regularly with all vertical leaders and project managers to understand project status, interdependencies, resource constraints, and technical risks.
Supervise and monitor all active R&D projects from architecture definition through tapeout, ensuring milestones are met and technical blockers are resolved promptly.
Facilitate cross-functional design reviews, tapeout readiness reviews, and silicon bring-up planning sessions to align all engineering verticals.
Serve as the primary technical escalation point for critical design issues, guiding root-cause analysis and resolution across SoC, analog, digital, physical, and DFT domains.
Stakeholder Communication & Reporting (10%)
Prepare and present comprehensive R&D project status reports, technical risk assessments, and resource utilization dashboards to senior leadership.
Interface with global counterparts, foundry partners (e.g., TSMC, GlobalFoundries), and IP vendors to optimize design flows and process node qualifications.
Other Duties (5%)
Champion R&D innovation initiatives; evaluate emerging technologies such as advanced packaging, chiplets, AI-driven EDA, and next-generation process nodes.
Support IP strategy, design reuse frameworks, and internal knowledge management across the India R&D center.
Undertake additional responsibilities as assigned by executive leadership.
MINIMUM QUALIFICATIONS
Bachelor's degree (B.E. / B.Tech) in Electronics & Communication Engineering, Electrical Engineering, VLSI Design, or a closely related field; Master’s degree (M.E. / M.Tech / M.S.) strongly preferred.
20+ years of progressive experience in the semiconductor / VLSI industry, with a minimum of 5 years in a senior engineering leadership or technical management role.
Proven, hands-on expertise across the complete chip design flow: SoC Architecture, Physical Design, Analog Design, Product & Test Engineering, Design Packaging, Verification Digital RTL Design, and DFT.
Demonstrated experience managing and delivering multiple concurrent chip design projects from specification through GDS tapeout.
Deep proficiency with industry-standard EDA tools: Cadence Innovus/Virtuoso, Synopsys Design Compiler/IC Compiler/PrimeTime.
Excellent written and verbal communication skills in English with demonstrated ability to present complex technical concepts to executive stakeholders.
DESIRED QUALIFICATIONS
Experience in leading R&D organizations of 25+ engineers across geographically distributed teams.
Exposure to advanced packaging technologies (2.5D/3D IC, chiplet architectures) and multi-die integration methodologies.
Familiarity with AI/ML-assisted EDA flows and next-generation design automation trends.
Prior experience with automotive-grade semiconductor design (AEC-Q100, ISO 26262 / ASIL compliance) or high-reliability industrial semiconductor products.
Strong publication record or patents in semiconductor design, device physics, or related fields.
Experience working with global foundry partners (TSMC, GlobalFoundries) on advanced process node qualification and PDK evaluation.
Demonstrated track record in building and scaling engineering teams; prior exposure to HR processes including headcount planning, compensation benchmarking, and performance management.