Sr. Staff Hardware Design Engineer
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsite andGlassdoor pages.
Job Description:
The Role
SiFive is seeking a Senior Hardware Design Engineer specialized in IOMMU (Input-Output Memory Management Unit) and Virtualization architectures. As RISC-V expands into data center, automotive, and high-performance computing (HPC) markets, the need for robust memory isolation and efficient virtualization is paramount.
In this role, you will lead the development of our MSI Translation Engine (MTE). While SiFive already designed a robust IOMMU IP, we are expanding our virtualization capabilities by designing a specialized MTE that leverages IOMMU-like mechanisms specifically for Message Signaled Interrupt (MSI) translation. This component is critical for RISC-V virtualization, as it ensures that interrupts from various high-speed peripherals (PCIe, AI accelerators) are securely translated and delivered to the correct Guest OS or Hypervisor context. You will work at the intersection of core MMU design and system-level interconnects
Leveraging our unique Chisel-based hardware generation framework, you will build highly configurable IP that scales from lightweight embedded systems to complex, many-core server-class SoCs.
Job Responsibilities
Micro Architecture & Design: Own the microarchitecture of the MSI Translation Engine, ensuring it meets strict latency and throughput targets for high-performance computing and automotive applications.
RTL Implementation: Develop RTL generators using Chisel (Scala), focusing on modularity and extreme configurability.
Memory System Optimization: Design and optimize the MTE's internal memory hierarchy, including TLBs, MSHRs, and local metadata caches.
Cross-Functional Collaboration: Work with Core MMU and Architecture teams to align MTE behavior with the RISC-V AIA (Advanced Interrupt Architecture) and H-extension specifications.
Verification & Physical Design: Partner with DV teams to create rigorous test plans for complex corner cases (e.g., page faults during interrupt translation). Collaborate with Physical Design to ensure timing closure on advanced process nodes.
Position Requirements
7+ years of industry experience in RTL design, specifically focusing on memory management, interrupt controllers, or complex SoC IP.
Deep Knowledge of Memory Systems: Proven experience with TLB design, MSHRs, cache controllers.
Virtualization Expertise: Strong understanding of IOMMU mechanisms, two-stage address translation, and hypervisor-level memory isolation.
Full RISC-V System with LTI (Look-aside Translation Interface): Experience with the RISC-V LTI protocol to offload address translation from the I/O device to the IOMMU/MTE, enabling efficient hardware-accelerated memory management in complex subsystems is a plus.
PCIe Knowledge very welcomed: Familiarity with the PCIe stack, specifically regarding ATS (Address Translation Services) and PRI (Page Request Interface), and how they interact with system-level translation engines.
Protocol Mastery: Expert-level knowledge of AMBA protocols, specifically AXI4.
Object-Oriented Programming: Proficiency in at least one OO or functional language (Scala, C++, or Java). Experience with Chisel/Scala is highly preferred.
Hardware Design Skills: Advanced proficiency in SystemVerilog or Verilog, with a focus on high-quality, maintainable code.
Communication: Must be fluent in English with the ability to document complex microarchitectural specifications clearly.
Education: MS/PhD in EE, CE, or a related technical discipline.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
FranceAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.