1,536,483open jobs
92,030companies
235,625added this week
Browse all
Salary
$165k – $270k per year
Location
In office (Redmond, Irvine, Austin, Palo Alto)
Seniority
Senior · 5+ years exp

Confirmed on the employer's own hiring board on Oct 12, 2026. First seen by Alion on Oct 1, 2026. SpaceX scores A on the Alion truth index.

Overview
Company
Impact
Profile match
SpaceX is an American aerospace manufacturer and launch services provider founded by Elon Musk in 2002 with the goal of making life multiplanetary. It developed the reusable Falcon 9, now by far the most flown orbital rocket in the world, the Dragon capsule that carries NASA astronauts to the International Space Station, and Starship, the fully reusable super-heavy vehicle intended for lunar and Mars missions. The company also operates Starlink, a satellite constellation of thousands of spacecraft providing broadband to consumers, aircraft, ships and militaries, which has become its largest source of revenue.

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)  

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

  • Ability to solve complex problems including clock domain crossings and power optimization
  • ASIC/SoC system integration experience
  • Experience with embedded CPU subsystems
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.)
  • Experience with high speed and low power design techniques
  • Scripting skills (e.g. Python, etc.)
  • Experience with EDA tools such as HDL simulators and HDL Lint tools
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION AND BENEFITS:

Pay Range:

Level 3: $165,000.00 - $270,000.00

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees in Washington State accrue paid sick time in compliance with state and federal law. Company shuttles are offered to employees for roundtrip travel from select Seattle locations to the SpaceX Redmond office Monday to Friday.

ITAR REQUIREMENTS:

  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to  [email protected]. 

Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
1,536,483 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Hardware
Similar stack
Same company
Redmond
$187k – $262k per year • Equity • In office • Bachelor's Degree • Torrance
Verilog
C
VHDL
MATLAB
C
Embedded C
MATLAB
Simulink
AI/ML
Quantization
Chips/EDA
Xilinx Vivado
HDL Coder
Vitis
Apply
$120k – $235k per year • In office • TS/SCI • 8+ years exp • Bachelor's Degree • Washington • Reston • Atlanta
DevOps
Azure
Management
OneDrive
Apply
$204k – $259k per year • Equity • Hybrid • Full-Time • 5+ years exp • Bachelor's Degree • Mountain View
Python
C++
SystemVerilog
DevOps
CI/CD
Chips/EDA
Cadence JasperGold
Formal Verification
Synopsys VC Formal
Apply
$159k – $196k per year • Equity • Hybrid • Full-Time • 5+ years exp • Master's Degree • Mountain View
Python
C++
MATLAB
Apply
$230k – $284k per year • Equity • Hybrid • Full-Time • 5+ years exp • Bachelor's Degree • Mountain View
Apply
≈ $72k – $127k per year (Estimated) • In office • 15+ years exp • Bachelor's Degree • Mississauga
Verilog
SystemVerilog
Apply
≈ $56k – $102k per year (Estimated) • In office • Full-Time • Bachelor's Degree • Grenoble • Sophia Antipolis
Python
Verilog
SystemVerilog
Perl
Chips/EDA
Tessent
Synopsys TestMAX
Apply
FPGA Engineer, EW 7 days ago
$146k – $194k per year • Equity • In office • Secret • 4+ years exp • Costa Mesa
Python
Verilog
SystemVerilog
VHDL
AI/ML
Computer Vision
Human-in-the-Loop
DevOps
CI/CD
Git
Linux
Robotics
Sensor Fusion
Apply
≈ $128k – $244k per year (Estimated) • Remote (likely United States) • 10+ years exp • Bachelor's Degree
Python
Verilog
C++
SystemVerilog
VHDL
DevOps
RTOS
CI/CD
HPC
Linux
Chips/EDA
UVM
Apply
$85k – $120k per year • In office • Full-Time • 3+ years exp • Bachelor's Degree • Upton
Python
Verilog
SystemVerilog
Perl
AI/ML
Ray
Apply
$165k – $240k per year • Equity • In office • 5+ years exp • Bachelor's Degree • Redmond
DevOps
Git
Bamboo
Gerrit
Linux
Wi-Fi
Apply
≈ $108k – $211k per year (Estimated) • In office • 3+ years exp • Bachelor's Degree • Bastrop
Apply
$100k – $135k per year • Equity • In office • 1+ year exp • Bachelor's Degree • Redmond
Python
Apply
$105k – $145k per year • Equity • In office • 1+ year exp • Bachelor's Degree • Redmond
Apply
≈ $148k – $278k per year (Estimated) • In office • 5+ years exp • Bachelor's Degree • Austin • Irvine • Palo Alto • Redmond
Python
Verilog
SystemVerilog
Apply
$129k – $175k per year • Equity • In office • Full-Time • Bachelor's Degree • Redmond
Apply
$135k – $175k per year • Equity • In office • 1+ year exp • Bachelor's Degree • Palo Alto • Irvine • Redmond
Python
Verilog
C++
SystemVerilog
VHDL
Chips/EDA
Synopsys SpyGlass
Xilinx Vivado
Apply
$175k – $280k per year • Equity • In office • 5+ years exp • Bachelor's Degree • Palo Alto • Irvine • Austin • Redmond
Python
Verilog
SystemVerilog
Apply
$155k – $172k per year • In office • Full-Time • 12+ years exp • Bachelor's Degree • Redmond • Seattle
Apply
$72k – $120k per year • In office • 5+ years exp • Redmond
DevOps
AWS
Management
Outlook
Microsoft Office
Apply
See all jobs
This is one of many
1,536,483 more open roles from verified company boards, updated every day.