Analog Design, Sr Staff Engineer - 17998

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ& PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed (>200Gbps) analog integrated circuits in the latest FinFETprocess nodes. Working from SerDes standards to block specifications, you quickly identifypotential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

You Are:

You are an accomplished analog design engineer with a passion for pushing the boundaries of high-speed connectivity. You thrive on solving complex technical challenges and are energized by collaborating with cross-functional teams to deliver best-in-class silicon solutions. Your expertisein SerDes and high-speed analog circuit design is complemented by your hands-on experience in developing, verifying, and optimizingcircuits for high performance, low power, and minimal area.

You are deeply familiar with the intricacies of CMOS design, and have a proven track record of successfully taping out silicon-proven designs for modern communication interfaces. You are detail-oriented, with a rigorous approach to design documentation and verification, and you communicate complex technical concepts with clarity to both peers and customers. You are comfortable navigating the entire design flow, from architectural review and specification through layout, simulation, and silicon validation. Above all, you are motivated by the impact your work has on the industry and on the innovative products that shape the world.

What You’ll Be Doing:

* Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.

* Identify and refine circuit implementations to achieve optimal power, area and performance targets.

* Developing and maintaining SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.

* Ownership of Analog Macro level design

* Review SerDes standards and architecture documents to develop analog specifications

* Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.

* Correlating simulated performance with silicon measurements to ensure accuracy and reliability.

* Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development and post-silicon.

* Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

What You’ll Need:

* M.Sc. or Ph.D. in Electrical or Computer Engineering with 6+ years of SerDes/High-Speed analog design experience.

* Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes

* Strong experience modeling circuits and systems in MATLAB/Simulink.

* Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.

* Proficiency in analyzing link budgets for PAM4 high-speed serial links.

* Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).

* Detailed design experience with several of the following SerDes sub-circuits:

receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC * Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.

* Knowledge of SPICE simulators and simulation methods.

* Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.

Who You Are:

* Innovative, analytical, and detail-oriented problem solver.

* Effective communicator with strong presentation and documentation skills.

* Collaborative team player who thrives in multidisciplinary environments.

* Motivated mentor and coach for junior engineers.

* Adaptable to changing project requirements and new technologies.

* Self-driven and committed to continuous professional development.

The Team You’ll Be a Part Of:

You will join a dynamic R&D team at Synopsys dedicated to developing high-performance serial-link transceivers for wireline and optical applications. The team is a blend of experienced analog and digital designers, hardware engineers, and system architects, united by a shared vision to advance silicon IP technology. Collaboration, creativity, and technical excellence are at the heart of our work, with a strong culture of mentorship and innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].