Applications Engineering, Sr Staff Engineer - 18828

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years working with formal verification tools and you know the difference between a tool that runs and a methodology that actually finds bugs before tapeout. You understand that formal is not magic, it is math applied with precision, and you are the kind of engineer who can look at a customer's design, their constraints, their timeline, and figure out where formal will save them and where it will not.

You are comfortable walking into a customer site, sitting down with their verification team, and quickly diagnosing why their formal runs are timing out or why their properties are not converging. You do not just recommend solutions, you build them alongside the customer, tuning assertions, refactoring testbenches, and optimizing performance until the tool does what it needs to do.

You think in trade-offs. You know when to push for full formal proof and when bounded checking is the right answer. You can explain complex formal concepts to a design engineer who has never written an SVA property, and you can hold your own in a technical debate with a verification architect who has been doing this for 20 years.

At Synopsys, you will work directly with customers deploying VC Formal across some of the most complex semiconductor designs in the industry. What you build and optimize will directly impact their verification closure and tapeout success.

What You'll Be Doing

• Lead formal verification methodology deployment at customer sites, working hands-on with their design and verification teams to integrate VC Formal into existing flows
• Assess customer design environments, identify high-value blocks for formal analysis, and define metrics that prove formal is delivering results
• Debug and resolve tool performance issues by analyzing design complexity, refining formal testbenches, and optimizing assertion modeling for convergence and runtime
• Develop and deliver technical training on VC Formal features, new releases, and best practices tailored to customer verification challenges
• Collaborate directly with Synopsys R&D and product engineering teams to communicate customer requirements, prioritize feature requests, and influence product roadmap based on field deployment experience
• Apply formal verification techniques across property checking, datapath verification, sequential equivalence checking, formal coverage analysis, connectivity checking, and specialized formal applications
• Serve as the technical bridge between customers and internal engineering, translating real-world verification problems into actionable product improvements

The Impact You Will Have

• Enable customers to close verification gaps that simulation alone cannot reach, reducing post-silicon bugs and accelerating time to tapeout
• Drive adoption of formal methodologies that become standard practice in customer verification flows, expanding the use of VC Formal across their design teams
• Improve tool performance and usability through direct customer feedback, shaping how VC Formal evolves to meet real-world deployment needs
• Build customer confidence in formal verification by delivering measurable results, proven methodologies, and hands-on technical partnership
• Reduce verification cycle time for complex designs by identifying the right formal techniques for the right problems at the right time
• Influence product direction by bringing field insights back to R&D, ensuring VC Formal remains aligned with customer priorities and industry trends
• Strengthen customer relationships through technical credibility, responsiveness, and a track record of solving hard verification problems

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
• 6+ years of hands-on experience in formal verification, including property checking, sequential equivalence checking, formal coverage, and connectivity checking
• Deep expertise with formal verification tools, ideally including VC Formal or equivalent platforms from other vendors
• Strong understanding of SystemVerilog Assertions (SVA), formal testbench modeling, and abstraction techniques for design complexity management
• Proven ability to debug tool performance issues, analyze convergence problems, and optimize formal runs for large, complex designs
• Experience working directly with customers or cross-functional engineering teams in a technical consulting, applications engineering, or field engineering role
• Solid grasp of RTL design, verification methodologies, and the semiconductor development lifecycle from architecture through tapeout

Who You Are

• You can walk into a customer meeting, listen to their verification pain points, and within an hour sketch out a formal methodology that addresses their specific challenges
• You are the person who does not give up when a formal proof times out, you dig into the design, refactor the environment, and find the abstraction that makes it converge
• You can explain why a certain property is vacuous to a junior engineer and then turn around and discuss formal engine algorithms with an R&D architect without missing a beat
• You are comfortable with ambiguity, customers will not always know what they need, and you are skilled at asking the right questions to uncover the real problem
• You push back when a customer asks for something that will not work, and you do it in a way that builds trust rather than friction
• You stay current with formal verification research, new techniques, and industry trends because you know this field moves quickly and standing still means falling behind

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.