ASIC Physical Design, Sr Engineer - 18393

Job Description and Requirements

Alternate Job Titles

• Physical Design Engineer
• ASIC Implementation Engineer
• Digital Physical Design Engineer
• RTL to GDS Engineer
• Backend Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years turning RTL into silicon that actually worksat 5GHz, not just in simulation, but in the lab when the first testchipcomes back. You know that a poorly planned power grid or a clock tree that looked fine in tool reports can kill a tapeoutthree weeks before the deadline, and you are the kind of engineer who sees those problems during floorplanning, not during signoff.

You are comfortable living in the Synopsys EDA toolchain, moving between Fusion Compiler for place and route, PrimeTimefor timing closure, and StarRCfor extraction without losing sight of what you are building: a high-speed interface IP that has to meet setup, hold, power, and area targets simultaneously. When a timing path fails by 200ps at a corner you were not expecting, you debug the netlist, check the constraints, talk to the RTL team if needed, and find the fix.

You care about methodology because a good flow means you iterate faster and catch issues earlier. Writing a TCL script that automates floorplan generation is not overhead,it is how you scale. At Synopsys, you will work on interface IP and testchipsthat go into AI accelerators, autonomous vehicle SoCs, and 5G infrastructure at 7nm, 5nm, and 3nm nodes.

What You'll Be Doing

• Drive complete digital implementation from RTL to GDS for high-speed interface IPs including Serdes, DDR, HDMI, MIPI, and USB at 7nm, 5nm, and 3nm nodes
• Execute synthesis, floorplanning, power planning, clock tree synthesis, placement, routing, and physical verification using Synopsys EDA tools
• Perform static timing analysis and close timing across multiple process corners, voltages, and operating modes
• Run EMIR signoff, analyze IR drop and electromigration, and iterate on power grid design to ensure reliable silicon operation
• Build physical design methodologies and automation scripts using TCL, Python, Perl, and Make to improve efficiency across projects
• Collaborate with RTL designers, verification teams, product engineers, and customers to ensure timely delivery and resolve technical issues
• Provide technical support to customers during IP integration and debug design issues as they arise

The Impact You Will Have

• Enable cutting-edge AI, autonomous vehicle, high-performance compute, cloud, 5G, and IoT applications by delivering silicon-proven interface IP
• Accelerate time to market for Synopsys customers by providing production-ready IP and testchipsthat integrate cleanly into advanced SoC designs
• Improve physical design quality across the IP portfolio by creating reusable methodologies and automation that scale across projects and process nodes
• Reduce design iteration cycles and signoff risk by catching timing, power, and physical issues early through disciplined analysis
• Strengthen customer confidence by delivering IP that works the first time in silicon and providing responsive technical support
• Contribute to Synopsys leadership in the interface IP market by pushing the boundaries of what is possible at 3nm and beyond

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 3+ years of hands-on experience in ASIC physical implementation, specifically RTL to GDS flows using industry-standard EDA tools
• Deep understanding of IC design fundamentals, physical implementation flows, and signoff methodologies for deep submicron designs
• Proficiency with industry-standard data formats including Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPF, and SPEF
• Strong scripting skills in TCL, Python, Perl, Unix Shell, and Make for automation and flow development
• Solid written and verbal communication skills in English for technical documentation and cross-functional collaboration
• Experience with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, or StarRCis a strong plus

Who You Are

• You can look at a floorplan and immediately spot the congestion hotspot or the power domain that is going to cause problems three steps downstream
• When a design fails timing by 500ps after routing, you step back, check the constraints, review the clock architecture, and figure out what actually needsto change
• You are comfortable explaining why a particular timing closure strategy will or will not work to product managers and IP architects without getting lost in tool settings
• You write automation scripts that other engineers can actually readand modify six months later

• You treat deadlines seriously, but you know when to flag a risk early rather than hoping it resolves itself during the next iteration

The Team You'll Be Part Of

You will join the Digital Implementation team, a group responsible for delivering high-speed, silicon-proven interface IP, testchips, and subsystem solutions at the latest process nodes. The team works on advanced technology supporting AI, autonomous vehicles, high-performance compute, cloud infrastructure, 5G mobile, and IoT applications.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.