Layout Design, Sr Engineer - 17737

Job Description and Requirements

Alternate Job Titles

• Senior Custom Layout Engineer
• IC Layout Senior Engineer
• Senior Memory Layout Designer
• FinFET Layout Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years drawing polygons that become transistors, cells, and eventually chips that power real products. Layout is not just about following design rules for you, it is about understanding why a certain spacing matters, why one routing choice will make a cell 15% faster, and why the circuit designer's intent can break if you miss a subtle boundary condition. You know that a clean DRC is the baseline, not the finish line.

You are comfortable sitting with a circuit schematic and translating it into a layout that balances density, performance, and manufacturability without being told exactly how. When an LVS fails, you do not just rerun the deck, you trace the mismatch back to the source. You have worked in FinFET nodes where the rules are dense and unforgiving, and you have learned to move quickly without cutting corners.

Collaboration matters to you. You ask questions when the spec is unclear. You flag risks early when a layout approach will not scale. You are the kind of engineer who automates the repetitive parts of your workflow so you can focus on the hard decisions, the ones that require judgment, not just tool execution. At Synopsys, you will work on memory and standard cell layouts that go into real IP used across the semiconductor industry.

What You'll Be Doing

• Design and integrate memory leafcell layouts and standard cell layouts using Custom Compiler, optimizing for area, speed, and power across advanced FinFET technology nodes
• Run and debug physical verification flows including DRC, LVS, ERC, and antenna checks using ICV, resolving violations down to clean tapeout-ready results
• Collaborate with circuit designers and verification engineers to ensure layout matches design intent and meets performance targets
• Build layout automation scripts in Perl, Shell, or TCL to accelerate repetitive tasks and improve consistency across design variants
• Optimize existing layouts for density and performance, identifying opportunities to shrink area or reduce parasitics without compromising reliability

The Impact You Will Have

• Deliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor markets
• Improve silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respins
• Accelerate project schedules by automating layout tasks and verification flows
• Raise the bar for layout quality across the team by sharing best practices and debugging techniques
• Enable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teams
• Help define layout methodologies that scale across multiple process nodes and design families

What You'll Need

• 2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design
• Deep familiarity with FinFET technology nodes and associated design rules, including complex spacing and enclosure requirements
• Proficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platforms
• Strong skills in DRC, LVS, ERC debugging, including resolving complex violations in hierarchical designs
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• Experience writing layout automation scripts in Perl, Shell, or TCL

Who You Are

• You approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisions
• You are detail-oriented without being slow, catching subtle issues while knowing when to move forward
• You communicate clearly with circuit designers and verification engineers, translating technical issues into actionable next steps
• You take ownership of your work, and if something breaks downstream, you want to understand why and prevent it from happening again
• You are curious and always learning, whether it is a new tool feature or a layout technique from a colleague

The Team You'll Be Part Of

You will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.