664,807open jobs
38,858companies
99,669added this week
Browse all
Salary
$53k – $130k per year (Estimated)
Location
In office (Catania)
Seniority
Intern
Employment
Internship
Overview
Company
Impact
Profile match
NXP Semiconductors is a Dutch chipmaker established in 2006 when Philips spun out its semiconductor division, and it concentrates on embedded processing rather than general purpose computing. Its largest market is automotive, where it supplies radar sensors, vehicle networking, battery management and the secure processors behind keyless entry and digital car keys, alongside industrial and internet of things microcontrollers, mobile secure elements and communications infrastructure silicon. Headquartered in Eindhoven and listed on Nasdaq, it is one of the leading suppliers of near field communication and automotive processing chips in the world.

NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.

NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design.

We are looking for an intern to support digital design activities within our growing Catania team, with hands-on project exposure, mentoring from experienced engineers, and potential university thesis collaboration.

Your Responsibilities

  • Support the development of digital sub-circuits related to complex System-on-Chip (SOC) designs based on pre-defined specifications, gaining hands-on exposure to RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), formal verification, power analysis, and design for testability (DFT) concepts.

  • Collaborate with analog, mixed-signal, digital, and software teams to understand interfaces, system performance considerations, and integration practices.

  • Follow established design methodologies and guidance from senior engineers to contribute to schedule commitments and quality objectives.

  • Assist with design verification activities using simulation tools and structured debug methodologies under the supervision of experienced engineers.

  • Contribute to lab, validation, and debug preparation activities, learning how design issues are identified, analyzed, and resolved to support product quality.

  • Prepare and maintain clear technical documentation, including design notes, verification summaries, and review material.

  • Learn industry trends, emerging technologies, and best practices in digital IC design methodology through project work and team mentoring.

Your Profile

  • Currently pursuing a Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

  • Basic knowledge of Verilog/SystemVerilog for RTL design and/or verification, gained through coursework, academic projects, or previous internships.

  • Familiarity with digital design flows and EDA tools is a plus, including RTL coding, synthesis, STA, or formal verification.

  • Understanding of basic digital design principles, with interest in areas such as clock domain crossing (CDC), low-power design, and SoC integration.

  • Exposure to scripting languages such as Python, Perl, or Tcl for automation is considered a plus.

  • Attitude to problem-solving, attention to details and ability to work in team oriented environment.

  • Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.

  • Curiosity, willingness to learn, and motivation to grow technical skills in a collaborative engineering environment.

-----------

NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.

More information about NXP in Italy...

-----------

#LI-8e4d
Free account
Stop reading job ads. Get the ones that fit.
One free account turns this page into a shortlist built around your stack, your level and your pay.
Match on every job. Stack, seniority, pay and location, scored against your profile.
664,807 open roles. Read straight off company career pages, refreshed every day.
Unlimited applications. Every one you send is tracked in one place, on-site or on a company board.
3 tailored CVs a month. Rewritten for the exact job you are applying to. Included free.
Create a free account Continue with Google
Free forever. No card. Under a minute.

Your match

How well do you fit this role?
Two answers are enough for a real match. No account needed.
Check my fit
Answers stay in this browser until you create an account.

Recommended for you based on this role

Similar stack
Same company
Catania
In office • 10+ years exp • Bachelor's Degree
Python
Verilog
C++
SystemVerilog
VHDL
DevOps
RTOS
CI/CD
HPC
Chips/EDA
UVM
Apply
$87k – $191k per year (Estimated) • In office • 3+ years exp • Bachelor's Degree • London
Verilog
SystemVerilog
Apply
$106k – $263k per year (Estimated) • In office • Internship • Bachelor's Degree • Richardson
Verilog
SystemVerilog
Apply
In office • 3+ years exp
Python
Verilog
SystemVerilog
VHDL
Perl
Chips/EDA
Synopsys SpyGlass
Synopsys PrimePower
Apply
$110k – $234k per year (Estimated) • In office • Full-Time • 5+ years exp • Bachelor's Degree • Canada
Python
SystemVerilog
Perl
DevOps
Git
Chips/EDA
UVM
Apply
$116k – $234k per year (Estimated) • Remote • Full-Time • 10+ years exp • Bachelor's Degree • United States
Management
Outlook
Apply
$110k – $234k per year (Estimated) • In office • Full-Time • 5+ years exp • Bachelor's Degree • Canada
Python
SystemVerilog
Perl
DevOps
Git
Chips/EDA
UVM
Apply
$25k – $55k per year (Estimated) • In office • Full-Time • 4+ years exp • Master's Degree • Bengaluru
Python
Java
IoT
FreeRTOS
Management
Agile
Apply
$33k – $72k per year (Estimated) • In office • Full-Time • Brno
Python
Apply
$51k – $128k per year (Estimated) • In office • Full-Time • 5+ years exp • Brno
Python
JavaScript
TypeScript
AI/ML
AI Agents
ONNX
TensorFlow
PyTorch
Frontend
React.js
DevOps
GitHub
Apply
$28k – $63k per year (Estimated) • Remote/Hybrid • Full-Time • Bachelor's Degree • Catania
Management
Outlook
Apply
$37k – $72k per year • In office • Part-Time • 1+ year exp • High School Diploma • Rome • Milan • Bari • Catania • Cagliari
Apply
$70k – $97k per year • In office • Full-Time • 12+ years exp • Bachelor's Degree • Catania
Python
Perl
Chips/EDA
Cadence Innovus
Synopsys PrimeTime
Synopsys Fusion Compiler
Siemens Calibre
Synopsys IC Validator
Cadence Pegasus
Ansys RedHawk
Apply
$36k – $50k per year • In office • Full-Time • Bachelor's Degree • Catania
Python
Perl
Chips/EDA
Synopsys Fusion Compiler
Cadence Voltus
Ansys RedHawk
Apply
$36k – $50k per year • In office • Full-Time • 2+ years exp • Master's Degree • Catania
Python
SystemVerilog
Perl
Chips/EDA
Cadence Xcelium
UVM
Apply
See all jobs
This is one of many
664,807 more open roles from verified company boards, updated every day.