R&D Engineering, Manager - 19519

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the last decade and a half deep in the physics and architecture of embedded memory, and you know that the difference between a compiler that ships and one that stalls is usually buried in how well someone understood variation, power, and area tradeoffs six months before tape-out. You have moved from designing circuits yourself to leading the people who design them, and you still get pulled into the hardest debug sessions because you can see what others miss.

Leading a team is not about delegation for you, it is about unblocking, teaching, and making sure your engineers have what they need to do their best work. You know when to let someone run with a problem and when to step in with a pointed question that changes the direction. You have managed projects across geographies, and you understand that keeping a distributed team aligned takes more than status meetings, it takes clarity, trust, and follow-through.

You do not wait for perfect information. When a layout is not converging or a characterization flow is producing questionable data, you dig in, ask the right people the right questions, and find a path forward. At Synopsys, you will lead a team building memory IP that powers the most advanced chips in the world, and the work you do will matter.

What You'll Be Doing

• Lead a team of engineers developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations across advanced FinFET nodes
• Oversee the full memory design flow from architecture definition through schematic entry, simulation, layout planning, verification, characterization, and model generation
• Drive low-power and area-efficient circuit design strategies, balancing performance, variation, and manufacturability constraints
• Coordinate with CAD teams on layout verification, parasitic extraction, and compiler automation using Perl and Python
• Manage project timelines, prioritize deliverables, and resolve technical and resourcing issues across multi-site teams
• Build and maintain relationships with internal stakeholders and external customers, translating technical requirements into executable design plans
• Mentor engineers on memory compiler development, transistor-level design, and advanced node challenges

The Impact You Will Have

• Deliver embedded memory IP that powers cutting-edge semiconductor products for Synopsys customers across AI, automotive, and high-performance computing
• Accelerate time-to-market for memory compilers by improving design flows, automation scripts, and characterization methodologies
• Enable your team to solve complex variation and power challenges in deep submicron and FinFET technologies, raising the technical bar across the organization
• Strengthen cross-functional collaboration between design, CAD, and verification teams, reducing integration friction and rework
• Build a high-performing, motivated team that consistently delivers on schedule and grows technically under your leadership
• Shape the roadmap for next-generation memory IP, influencing architecture decisions that affect product competitiveness
• Contribute to Synopsys' reputation as a trusted partner by delivering robust, scalable, and customer-focused memory solutions

What You'll Need

• BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from a recognized institute or university
• 15+ years of hands-on experience in embedded memory design, including SRAM, Register File, TCAM, or ROM
• Deep expertise across the full memory design flow: architecture, circuit design, layout, compiler automation, characterization, timing, and model generation
• Proven experience leading engineering teams and delivering complex projects on schedule in a multi-site environment
• Strong proficiency in Perl and Python for design automation and scripting
• Hands-on experience with deep submicron and FinFET technologies, including variation-aware design techniques
• Solid understanding of CMOS fundamentals, digital design, RC circuits, transfer function analysis, and CMOS fabrication processes

Who You Are

• You can walk into a layout review, spot the issue that is going to cause a timing violation three steps downstream, and explain the fix in a way that gets the team moving again
• You manage multiple projects and shifting priorities without losing track of what matters most, and you communicate risks and tradeoffs clearly before they become blockers
• You build trust across teams by following through, showing up when things get hard, and giving credit where it belongs
• You know how to have the tough conversation when a design is not going to meet spec, and you do it early enough that the team has options
• You mentor engineers not by giving answers but by asking the questions that help them think through the problem themselves
• You stay current on memory design trends, advanced node challenges, and industry best practices, and you bring that knowledge back to your team

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.