R&D Engineering, Sr Staff Engineer - 19091

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of custom layout, where a single misplaced contact can derail a tapeout and where DRC clean means nothing if the circuit doesn't perform. You know the difference between a layout that works on paper and one that survives across process corners, and you have debugged enough blocker issues at 2am to understand what customers actually need when they say "it's urgent."

You are equally comfortable sitting with a foundry layout team walking through a migration flow as you are sitting with R&D explaining why a specific customer design rule is breaking their methodology. You do not just escalate problems, you own them until they are resolved, whether that means writing a SKILL script, building a workaround, or getting on a plane.

Migration work excites you because it is never clean. Node-to-node and fab-to-fab analog IP migration means dealing with incomplete PDKs, shifting design rules, and customers who need it working yesterday. You have done this before and you know how to build flows that actually scale beyond the first test case.

At Synopsys, you will work directly with the largest semiconductor companies in Korea on the most advanced nodes in production today. What you enable will ship in products that matter.

What You'll Be Doing

• Own Custom Compiler technical engagement at leading Korean foundry, memory, and fabless customers, driving tool deployment, methodology adoption, and advanced-node enablement on their most critical custom layout projects
• Lead on-site debug and root-cause analysis for blocker issues, working directly with customer layout teams and Synopsys R&D to deliver patches, workarounds, and hotfixes aligned to customer tapeout schedules
• Develop and validate node-to-node and fab-to-fab analog IP migration methodologies, building production-ready flows that scale across multiple process nodes and customer design environments
• Drive adoption of layout synthesis using ASO.ai and other Synopsys.ai solutions, integrating them into customer workflows and proving out ROI on real customer designs
• Build and deliver methodology decks, application notes, training materials, and customer-facing workshops that translate complex tool capabilities into actionable flows for layout engineers
• Validate new Custom Compiler features on customer reference designs at advanced nodes, providing feedback to R&D on what works, what breaks, and what needs to change before general release
• Partner with field application teams and R&D to define product roadmap priorities based on direct customer engagement, ensuring that what we build next is what these customers actually need

The Impact You Will Have

• Enable leading Korean foundry, memory, and fabless customers to adopt Custom Compiler and layout synthesis on their most advanced nodes, directly accelerating their time to tapeout and reducing manual layout effort
• Unblock critical customer tapeouts by resolving tool and methodology issues that would otherwise delay production schedules by weeks or months
• Build migration flows that allow customers to reuse analog IP across nodes and fabs, protecting millions of dollars in prior design investment and reducing redesign cycles
• Shape the Custom Compiler product roadmap by feeding real customer requirements and pain points directly into R&D, ensuring that future releases solve the problems that matter most to our largest accounts
• Establish Synopsys as the trusted technical partner for custom layout at Korea's leading semiconductor companies, strengthening customer relationships and driving long-term tool adoption
• Accelerate industry adoption of AI-driven layout synthesis by proving out ASO.ai on production designs, demonstrating measurable productivity gains that change how layout teams work
• Train and enable dozens of customer layout engineers through workshops and direct engagement, multiplying your impact across entire design organizations

What You'll Need

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 7+ years of hands-on experience in custom IC layout for analog, mixed-signal, memory, standard cell, or IP blocks, or in EDA Product Engineering or Application Engineering supporting custom layout tools
• Proficiency with Synopsys Custom Compiler or Cadence Virtuoso, including deep familiarity with layout editors, design rule checking, LVS flows, and parasitic extraction
• Strong understanding of advanced-node design rules, physical verification flows, and parasitic-aware layout techniques for advanced-node
• Scripting capability in SKILL, Python, or Tcl, with comfort working in Linux/Unix environments to automate flows and debug tool issues
• Fluency in Korean and strong English communication skills, with the ability to present technical content to customer executives and lead workshops for engineering teams
• Experience with analog IP migration across process nodes or foundries, or hands-on work with layout synthesis tools, is a strong differentiator

Who You Are

• You can walk into a customer war room with a broken flow and walk out three hours later with a working patch and a plan, not just a ticket number
• Ambiguity does not slow you down. When a customer says "the migration flow isn't working," you know how to narrow that down to a specific design rule conflict, a tool bug, or a methodology gap without needing perfect information upfront
• You push back when a proposed solution will not scale. If a workaround works for one test case but will break on real customer designs, you say so and propose an alternative, even if it takes longer
• You can explain a complex layout synthesis tradeoff to a customer VP in two sentences without losing the technical nuance, and then turn around and debug a SKILL script with their layout team
• Travel to customer sites does not phase you. You are comfortable spending time on-site in Korea, working directly with customer teams in their environment, on their schedules
• You care about the details that make the difference between a demo and a production flow, the edge cases, the performance at scale, the integration points that break under real-world conditions

The Team You'll Be Part Of

You will be part of the Custom Compiler Product Engineering team, working closely with R&D in multiple geographies and with field application engineers supporting Korea accounts. This role is customer-facing and requires deep collaboration with leading Korean foundry, memory, and fabless layout and CAD teams. You will also work directly with the Synopsys.ai team on layout synthesis adoption and methodology development.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.