DV with PCIE Engineer

Role: Engineer. Skills: VLSI. Experience: 6 - 8 Years. Qualification: Bachelor Of Engineering

Must-Have**

(not more than 3-5)

• "We

are looking for a highly motivated and skilled Design Verification Engineer

to join our verification team. The ideal candidate should possess strong

expertise in SystemVerilog, UVM, AXI, and PCIe protocols, along with solid

knowledge of verification methodologies and debug techniques.

• The

candidate should also be comfortable leveraging AI tools, prompt engineering,

and automation techniques to improve verification productivity and accelerate

debug cycles.

• The

selected candidate will be responsible for developing scalable verification

environments, creating comprehensive verification plans, driving coverage

closure, debugging complex issues, and collaborating closely with design,

firmware, and architecture teams.

1

Verification Planning & Execution

2

Develop detailed verification plans based on design and

architectural specifications.

3

Build reusable and scalable verification environments

using SystemVerilog and UVM.

4

Create and execute directed, constrained-random, and

stress test scenarios.

5

Drive functional, code, assertion, and toggle coverage

closure.

6

Ensure high-quality verification sign-off for complex IP

and SoC subsystems.

7

Protocol Verification

8

Verify industry-standard protocols including:

9

AXI4 / AXI4-Lite / AXI-Stream

Required

Technical Skill Set**

DV with PCIE

Desired

Experience Range**

6 - 12years

Location

of Requirement