Design Verification (DV) Engineer

Job Description

• Skill Set :

  VLSI Design Verification Debug

• Total Experience :

  5.00 to 10.00 Years

• No of Openings :

  1

• Job Post Date :

  06/11/2026

• Job Expiry Date :

  09/12/2026

• Domain :

  IT

• Location :

  SAN JOSE [United States]

• Job Reference No :

  4117016

Job Summary

Job Title: Design Verification (DV) Engineer

Location: Boston, MA

Onsite/ Remote: Remote/Hybrid

The pay range for this role is $125k- $145k per annum including any bonuses or variable pay. Tech Mahindra also offers benefits like medical, vision, dental, life, disability insurance and paid time off (including holidays, parental leave, and sick leave, as required by law). Ask our recruiters for more details on our Benefits package. The exact offer terms will depend on the skill level, educational qualifications, experience, and location of the candidate.

JD:

Good hands on experience in verification with C or C++.

Senior DV engineers that have substantial experience with C++.

C++ will be used verification (via teal/truss) and not SV/UVM

Ideally, the candidates would have experience with either DSP and/or Ethernet protocols.

“Tech Mahindra is an Equal Employment Opportunity employer. We promote and support a diverse workforce at all levels of the company. All qualified applicants will receive consideration for employment without regard to race, religion, color, sex, age, national origin, or disability. All applicants will be evaluated solely based on their ability, competence, and performance of the essential functions of their positions with or without reasonable accommodations. Reasonable accommodations also are available in the hiring process for applicants with disabilities. Candidates can request a reasonable accommodation by contacting the company ADA Coordinator at [email protected].”