Lead Engineer

We are pleased to reach out to you regarding a potential opportunity for the position of Lead Engineer.

Job Description:

• Lead and execute memory subsystem and LPDDR validation activities across post-silicon environments.
• Develop validation strategies, test plans, test cases, and coverage plans for memory controllers, PHY, and LPDDR interfaces.
• Perform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing, and functional testing.
• Validate different memory configurations, frequencies, data rates, channels, ranks, and memory densities.
• Debug memory-related failures at SoC, controller, PHY, firmware, and board level.
• Work closely with hardware design teams to understand memory controller, PHY, clocking, reset, power, and interface architecture.
• Review hardware design specifications, block diagrams, schematics, and relevant design documentation.
• Support silicon bring-up, memory initialization, and platform-level validation.
• Develop and maintain automation scripts for validation, debug, and data collection using Python, Shell, or similar scripting languages.
• Validate memory reliability, stability, and performance under different system workloads.
• Mentor junior engineers and provide technical guidance to the validation team.
• Lead technical discussions with internal teams and customers and communicate project status, risks, and dependencies.

Experience:

• Strong experience in memory subsystem validation and debug.
• Hands-on experience with LPDDR4/LPDDR4X/LPDDR5/LPDDR5X.
• Good understanding of memory controller architecture, DDR/LPDDR PHY, read/write leveling, memory channels, ranks, and banks, ECC, and memory error handling.
• Strong knowledge of post-silicon validation and silicon bring-up.
• Experience in debugging failures across hardware, firmware, and software layers.
• Ability to read and understand schematics, block diagrams, and hardware specifications.
• Good understanding of system-level interfaces such as PCIe, USB, I2C, SPI, UART, JTAG, etc. is an added advantage.
• Understanding of SoC and memory subsystem architecture.
• Understanding of memory controller and PHY integration.
• Reading and analyzing schematics and board layouts.
• Lead a team of validation engineers and own technical deliverables.
• Define validation priorities, execution plans, and debug strategy, and review test plans, test cases, automation, and debug reports.
• Mentor team members on memory validation and hardware debug methodologies.
• Good communication and interpersonal skills.

Skills

LPDDR, Lpddr4, Lpddr4X, Lpddr5, Lpddr5X, Python, Shell, Validation