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Analog Design Engineer

Texas Instruments • Bachelor's Degree • Verilog • 3 months ago

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Salary

≈ $15k – $35k per year (Estimated)

Location

In office (Bengaluru)

Seniority

Junior · 2+ years exp

Confirmed on the employer's own hiring board on Oct 11, 2026. First seen by Alion on Jul 16, 2026.

Overview

Company

Impact

Profile match

Texas Instruments

Headquartered in Dallas, Texas, Texas Instruments is a global semiconductor design and manufacturing company that develops analog chips and embedded processors. The firm serves tens of thousands of customers worldwide, helping them create advanced electronics for industrial, automotive, personal electronics, and enterprise markets. Through continuous innovation in semiconductor technology, the corporation plays a pivotal role in shaping modern electronic systems and power management solutions.

ti.com • HQ: Dallas, United States • Semiconductor Manufacturing • Processors, MCUs & AI Chips • Analog & Power Semiconductors • 501-1000 employees • Est. 1930

Tech stack of Texas Instruments

Backed by NEA, Lightspeed Venture Partners

Change the world. Love your job.

Texas Instruments (TI) is out front and ready for the next big challenge. Our innovations are at the core of nearly every electronics product in use today. And it doesn't stop there. We're developing breakthrough technology to power the world's future innovations as well. TI is committed to building a better future - from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. Put your talent to work with us.

This is a great opportunity to be part of an established team that's continuing to look for growth opportunities, working with worldwide leading customers and developing cutting edge solutions in the areas of consumer electronics, mobile computing and communications.

In this role, responsibilities may include:

Design of I/O circuits like GPIOs (failsafe, non-failsafe), level shifters, LVDS I/O, bandgap, LDO, multi-voltage buffers etc and optimize for power/performance/area
Ensure design robustness through comprehensive PVT corner simulations, reliability analysis, monte carlo analysis.
Post layout simulations and ability to debug and provide guidance to the layout engineer as needed
Detailed analysis and documentation of the verification data
Understanding and providing inputs on dotlibs, verilog, Ibis data generation
Collaborate with cross functional team to enable seamless integration of IP at SoC

Minimum requirements:

Bachelor's degree in Electrical Engineering
2 years of relevant experience

Preferred qualifications:

Strong understanding of CMOS transistors, short channel effects etc.
Experience in design of I/O types (Failsafe and Non-Failsafe), multi-voltage design, LVDS
Knowledge of ESD protection schemes, I/O standards, dotlibs, verilog, IBIS
Optimize I/O for performance, power, area
Able to run comprehensive PVT corner simulations, reliability analysis, monte carlo analysis, and signal integrity checks (crosstalk/ISI)
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Ability to quickly ramp on new systems and processes
Demonstrated strong interpersonal, analytical and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Ability to take the initiative and drive for results
Strong time management skills that enable on-time project delivery