Senior Layout Engineer

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future - from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us - change the world, love your job! Who are we and what do we do?

The advanced circuits and power solution business is known for delivering industry leading custom IC system solutions including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices and high-performance communication interface products. Our products integrate precision signal-chain and highly efficient power components in ultra-small form factors that enable TI’s best-in-class customer to translate their ideas to high value products that revolutionize the personal electronics market.

In this team, you will get to work with, and learn from incredibly talented technical leaders, who have influenced TI technology, productivity and way of working in a creative and impactful way. You will get to directly interact with one of TI’s valued and high-volume customers, by way of intense technical reviews and architecture discussions!

By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.

Location: Bangalore, India

Experience: 3-10 Years

Roles and responsibilities:

• Frame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project
• Work closely with designers to understand the architecture and key requirements for the IC
• Strike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams
• Work closely with Process development team to carry out PDK, P-cell and Design rule updates
• Work closely with Packaging engineer to develop custom lead-frames for various packages
• Analysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic
• Routinely develop test vehicles for new process & package technology development
• Mentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms
• Responsible for the final layout which meets the design expectations and layout checklist.
• Identify improvements needed in process/ quality/ cycle time and take up necessary initiatives

Knowledge and skills:

• Full chip layout experience from definition through release of IC to production
• Strong LVS, DRC, ERC, and antenna debug skills
• Proficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques
• Good understanding about all layout parasitics (R, C, diodes, BJTs)
• Good understanding of device physics and semiconductor fabrication process
• Must have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD
• Should be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas
• Ability to quickly ramp up on new tools/ process and mentor LEs
• Experience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage
• Requires excellent teamwork, good communication, strong problem-solving and documentation skills.
• Strong time management skills for on-time project delivery
• Ability to take initiatives and drive for results