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Salary
≈ $15k – $34k per year (Estimated)
Location
In office (Malacca)
Seniority
Senior · 5+ years exp

Confirmed on the employer's own hiring board on Oct 15, 2026. First seen by Alion on Oct 15, 2026. Texas Instruments scores B on the Alion truth index.

Overview
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Headquartered in Dallas, Texas, Texas Instruments is a global semiconductor design and manufacturing company that develops analog chips and embedded processors. The firm serves tens of thousands of customers worldwide, helping them create advanced electronics for industrial, automotive, personal electronics, and enterprise markets. Through continuous innovation in semiconductor technology, the corporation plays a pivotal role in shaping modern electronic systems and power management solutions.

Packaging Engineer

About TI

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future - from the responsible manufacturing of our semiconductors to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us - change the world, love your job!

About the job

As a Packaging engineer you will enjoy an environment of smart collaboration with a global team of the industry’s top engineering minds at your disposal. TI’s corporate culture is one of competitive spirit which fuels continued business growth and constant career opportunities. While ethical business practice is a central aspect of the work place-you will be treated with respect, dignity, kindness and courtesy.

Put your talent to work with us as a Packaging engineer - change the world, love your job!

Responsibilities include:

  • Hands on or optimizing FOL process such as Face2Face Flip Chip & Reflow process as well as swivel molding characterization for dual side cooling MCM package
  • Defining simplified FOL and EOL manufacturing process sequence for power stage package
  • Managing multiple new product executions starting from kick-off, product prototyping, characterization, learning cycles, and qualifications until product released with engineering approach such as JMP analysis, FMEA, control plan, etc.
  • Collaborate closely with factory operations teams to meet manufacturing indices, quality standards, and cost entitlements
  • Engaging with global package platform and emerging technology team to execute differentiated technology roadmaps to establish process capabilities in front of needs
  • Enabling TI MCM modules package competitiveness through adopting the industry latest greatest capabilities and maximize package design flexibility for adapting the latest technology.
  • Work with multi function to enable stress modeling to understand the package design weak point and define the contingency plan to overcome it.

Minimum requirements:

  • Bachelor’s Degree in Mechanical Engineering, Physics, Material Science, or a related field of study
  • Cumulative > 3.3 CGPA and above
  • Minimum 5 years-experience in the manufacturing semiconductor field
  • Expert level experience in process development for power stage, multi chip module
  • Package layer design expertise such as structural configuration, material selection and process flow design
  • Hands on skills in operating machines and knowledge to down-select material, process optimization and yield improvement
  • Expert experience of using ANSYS / FEA for stress modeling

Preferred qualifications:

  • Ability to engage with a geographically diverse team with a strategic vision to drive a complex technology roadmap.
  • Hands on experience on system-in-Package (SiP), including multi chip package or package on package is added advantage.
  • Knowledge of power stage packaging design, including understanding of Design for Manufacturability (DFM) constraints and defect criteria.
  • Experience in multi-process coordination and optimization (integration between SMT and back-end packaging processes)
  • Ability to establish strong and collaborative relationships with stakeholders, global design & manufacturing teams and component/material/substrate supplier to meet on-time execution
  • Broad and deep technical understanding of leadframe / DBC / MIS manufacturing.
  • Knowledge in FMEA methodology, process control plan, statistical analysis, SPC and DOE methodology. Skilled in JMP statistical analysis software is an added advantage
  • Experience with assembly of power modules packaging, substrate design and reliability requirements
  • Project management experience in semiconductor industry specifically in Assembly Test or SMT Operation
  • Key personal characters - trustworthy, inclusive, innovative, competitive, result-oriented
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