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Location
In office (Bengaluru)
Seniority
Middle · 3+ years exp

Confirmed on the employer's own hiring board on Oct 24, 2026. First seen by Alion on Sep 22, 2026. Texas Instruments scores B on the Alion truth index.

Overview
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Profile match
Headquartered in Dallas, Texas, Texas Instruments is a global semiconductor design and manufacturing company that develops analog chips and embedded processors. The firm serves tens of thousands of customers worldwide, helping them create advanced electronics for industrial, automotive, personal electronics, and enterprise markets. Through continuous innovation in semiconductor technology, the corporation plays a pivotal role in shaping modern electronic systems and power management solutions.

About ASM Auto:

ASM (Application specific Microcontroller) business powers automotive and industrial MCU across multiple applications. ASM is now working on next generation Automotive MCU platform for all kind of vehicle applications e.g. Traction motor control, Charging, Lighting and Heating control, IC Engine management etc. This platform will churn out multiple differentiated products for Zonal networking in Software defined Vehicles (SDV) and superior real time control for EV Cars. Great opportunity to be part of this grounds up platform development across process nodes, IPs and SoCs.

https://www.ti.com/applications/automotive/overview.html

What will you be doing in this role as a STA Engineer?

As an STA engineer in the team, you will be part of the STA team responsible for analysis and timing closure of the automotive MCU Cores.

What do we expect from you?

  • Bachelor or Master’s degree in Electrical engineering.
  • 3+ years’ experience in STA roles
  • Experience with constraints development of block level designs and at the chip level too
  • Good understanding of concepts like:
    • Margins, OCV, timing corners
    • Group and Path based analysis
    • Functional and Test Mode constraints merging
    • IO STA: Deriving constraints from chip/protocol interface specs and analysis
    • ILM/ timing models for blocks
    • Crosstalk analysis
  • Hands on working experience with one or more of the below areas:
    • Experience with planning, setting up and managing the STA runs for design (preferably at the chip level)
    • Experience with analysis of reports, deriving fixes and working with the PD team to drive the timing ECOs
    • Working with DFT team to understand the DFT architecture and help derive the test mode constraints
  • Good working knowledge of timing signoff tools like Primetime or Tempus
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