Senior DFT Engineer

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are looking for a Senior DFT Engineer with solid hands-on experience to own key aspects of DFT implementation and verification for advanced SoC designs. You will drive DFT features to achieve high test coverage while optimizing for test time and power.

WhatYou’llDo

• Develop and implement DFT architecture including scan insertion, compression, and hierarchical DFT.
• Generate and optimize ATPG patterns for various fault models (stuck-at, transition, path delay, etc.) and perform failure diagnosis.
• Design, integrate, and verify MBIST controllers, repair mechanisms (BISR), and memory test strategies.
• Implement and verify Boundary Scan (BSCAN), JTAG, and IJTAG (IEEE 1687) infrastructure.
• Perform DFT static timing analysis (STA), constraint development, and timing closure in collaboration with PD teams.
• Execute DFT verification including pre-silicon simulations and Gate-Level Simulation (GLS).
• Support silicon bring-up, ATE (Automated Test Equipment) pattern validation, and post-silicon debug.
• Work closely with cross-functional teams (RTL, Verification, Physical Design, Test Engineering) to resolve DFT issues.
• Analyze coverage metrics and improve test quality.

WhatWe’reLooking For

• Bachelor’s/Master’s degree in Electronics/Electrical Engineering.
• 4-7 years of experience in DFT for SoC/ASIC designs.
• Strong proficiency inATPG, MBIST, LBIST, scan compression,BSCAN and IJTAG.
• Experience with industry tools for DFT insertion, pattern generation, and simulation.
• Hands-on silicon bring-up and debug experience.
• Proficiency in scripting (Python,Tcl, Perl) for automation.