Staff DFT Engineer

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are hiring aStaff DFT Engineer to lead DFT strategy, architecture, and implementation for complex, high-performance SoCs. You will define methodologies, and drive DFT from RTL to silicon bring-up, ensuring optimal quality, cost, and time-to-market.

WhatYou’llDo

• Define DFT architecture and test strategy for SoCs, including scan, compression, MBIST, LBIST, and IO test.
• Lead ATPG pattern generation, optimization, and diagnosis flows across multiple fault models.
• Architect and oversee MBIST, BISR, and memory repair solutions for large memory arrays.
• Design and implement advanced test access mechanisms using JTAG, Boundary Scan (BSCAN), and IJTAG (IEEE 1687).
• Drive DFT timing closure, power-aware DFT, and hierarchical/multi-core test strategies.
• Own pre-silicon DFT verification (ATPG simulation, GLS) and coverage closure.
• Lead silicon bring-up, ATE test program development, post-silicon validation, debug, and yield improvement.
• Collaborate with cross-functional teams to integrate DFT into the overall design flow and resolve complex issues.
• Mentor junior and mid-level engineers; contribute to methodology development and tool evaluation.
• Optimize test time, data volume, and manufacturing test costs.

What We’re Looking For

• Bachelor’s/master’s degree in Electronics/Electrical Engineering.
• 8+ years of strong hands-on experience in DFT for complex SoC/ASIC projects.
• Expert-level knowledge of ATPG, MBIST, LBIST, IJTAG, BSCAN, scan compression, and related areas.
• Proven track record in silicon bring-up, ATE support, and post-silicon debug.
• Deep understanding of full ASIC flow (RTL to Silicon) and DFT impact on PPA.
• Proficiency with leading EDA tools (Synopsys TetraMAX/DFTMAX, Siemens/Tessent SSN, TestKompress etc.).
• Strong scripting and automation skills.

Good To Have

• Knowledge of advanced topics like 2.5D/3D packaging test, analog/mixed-signal DFT.

Job Location

Hybrid/ On-site - Bangalore / Remote - India