Staff Firmware & System Software Engineer — Platform Controller and SoC Stack

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

About the role

We are building the software stack that runs on next-generation silicon. Based on Zephyr-platform management controller responsible for secure boot, system software on the application processor - bootloader, kernel drivers, PCIe subsystem, and IOMMU configuration - that turns raw silicon into a platform an operating system can run on.

What you’ll do

Firmware and platform control

• Design, implement, and maintain Zephyr RTOS firmware for a platform management controllers, including device drivers, subsystem integration, and application-level services.

• Write and upstream-quality-review drivers against Zephyr's driver model - devicetree bindings, Kconfig, init levels and priorities, struct device APIs.

System software and high-speed interconnect

• Bring up and debug PCIe links on first silicon - LTSSM progression, link training failures, lane reversal and polarity, equalization, speed and width negotiation.

• Implement and maintain PCIe host controller and endpoint drivers: enumeration, configuration space, BAR allocation, MSI/MSI-X interrupt routing, AER and error handling, ASPM and link power states.

• Configure and validate IOMMU behavior - address translation, DMA remapping, device isolation domains, page-table management, fault reporting and recovery.

• Develop system software across the boot and runtime path: bootloader, firmware-to-OS handoff, ACPI or device tree description, kernel drivers, and the DMA and memory-management interfaces they depend on.

• Debug DMA correctness and coherency problems end to end, from device transaction through translation to system memory.

Silicon and process

• Perform post-silicon bring-up: first-boot debug, clock and reset validation, bus enumeration, triage of RTL-versus-firmware ambiguity with design teams.

• Debug hard problems using JTAG/SWD, ETM/ITM trace, protocol analyzers, and logic analyzers - including intermittent, timing-dependent, and multi-master failures.

Required qualifications

• 8-10 years of professional embedded firmware and/or system software development in C, with meaningful exposure to modern C++ or Rust.

• Deep, hands-on RTOS experience on 32-bit microcontrollers (Arm Cortex-M or RISCV) scheduling, priority assignment, ISR design, synchronization primitives, and the failure modes each one produces.

• Proven driver development experience against a formal driver model, including bus drivers and interrupt-driven peripherals.

• System software fundamentals: virtual memory and address translation, DMA and cache coherency, the kernel/users pace boundary, and how a platform gets from reset vector to a running OS.

• Working knowledge of PCIe architecture - enumeration, configuration space, BARs, MSI/MSI-X, and the transaction model - sufficient to debug why a device is not appearing or not moving data.

• Understanding of what an IOMMU is for and what it costs: translation, isolation, and the DMA failure modes that appear when it is misconfigured.

• Demonstrated ability to read a hardware specification or register map and translate it into correct, testable software without handholding.

• Applied AI/ML knowledge - Strong AI based coding.

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

Preferred qualifications

Strong candidates will have direct experience with several or some of the following.

· PCIe and interconnect

· IOMMU and virtualization

· System software

· RTOS and platform

· Peripherals and subsystems