Design verification Engineer

Uniconnect • C++ • SystemVerilog • 2 years ago
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Salary
≈ $18k – $46k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Senior · 5+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 27, 2026. First seen by Alion on Feb 21, 2024. Uniconnect scores D on the Alion truth index.

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Uniconnect

Looking for the Top Semiconductor and AI Acquisition Firm in Singapore? UniConnect is your trusted job agency for recruitment solutions in Singapore.
uniconnect.com.sg • Bengaluru • Hyderabad • George Town • Bayan Lepas • Coimbatore • Professional Services • Recruiting & Staffing
  • Experience in C/C++ programming is desirable.
  • Good communication skills
  • Excellent hands on Debug Skill is must.
  • Must have experience in developing test bench / test case using System Verilog & UVM.
  • Must have experience in functional coverage & assertions development.
  • Knowledge of system-level architecture including buses like AXI/AHB, bridges is a must.
  • Experience in any Processor or protocols is a must.
  • Self-motivated

Requirements

5+ years of experience in IP or SOC Verification.

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