DFT Engineer

• Perform

  ATPG pattern generation including SSA /Transition/RSQ Path Delay and IDDQ

  pattern using Siemens Tessen tools

• Perform

  ATPG verification and simulation playback using Synopsys/ Cadence simulator

• Strong

  Analytical mindset and simulation debug capabilities to resolve simulation

  mis-match

• Good

  design knowledge needed that can help improve the test coverage the low

  coverage of a design

• Deliver

  high quality ATE patterns for production ATE testing

• test pattern support to ATE engineering team for First Proto bring up and

  failure analysis in the use of ATPG test and scan/debug features

Requirements

• Bachelor degree or equivalent in Electrical or

  Computer Engineering

• 3 to

  5 years DFT working experience

• Familiar

  with HDL design language

• Good

  working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell,

  Perl)

• Knowledge

  of ASIC design is a must, and ATE test is a plus

• Strong

  problem solving skills

• Team

  player with strong communication skills

• Number of Vacancy - 2