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Salary
≈ $39k – $79k per year (Estimated)
Location
In office (Singapore)
Seniority
Senior · 6+ years exp
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 24, 2026. First seen by Alion on Dec 17, 2024. Uniconnect scores D on the Alion truth index.

Overview
Company
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Looking for the Top Semiconductor and AI Acquisition Firm in Singapore? UniConnect is your trusted job agency for recruitment solutions in Singapore.

Job Responsibilities:

  • Perform

    detailed STA on digital designs used in networking and audio

    solutions at various stages of the IC design flow (pre-layout,

    post-layout).

  • Identify, analyze, and

    resolve timing violations in critical paths, ensuring low latency and high

    throughput for networking and audio processing applications.

  • Conduct multi-mode,

    multi-corner (MMMC) analysis to ensure timing closure under different

    operating conditions, including power-saving modes.

  • Develop, validate, and

    optimize timing constraints tailored for high-speed networking interfaces

    and high-fidelity audio processing circuits.

  • Define and validate

    clock definitions, I/O constraints, multi-cycle paths, and false paths,

    ensuring robust performance in real-world applications.

  • Work closely with the

    Physical Design team to address timing issues, suggest optimizations, and

    support clock distribution for complex networking and audio processing

    circuits.

  • Perform final timing

    analysis and sign-off, ensuring that our ICs meet stringent timing, area,

    and power requirements for networking and audio applications.

  • Work with post-silicon

    validation teams to correlate timing models with actual silicon

    measurements, ensuring that our networking and audio solutions perform as

    expected in the field.

Requirements

Requirements:

  • Bachelor’s or Master’s

    degree in Electrical Engineering, Computer Engineering, or a related

    field.

  • 6+ years of experience

    in STA for digital ICs, preferably in the networking or audio

    domain.

  • Strong understanding of

    digital design principles, timing concepts, and semiconductor physics.

  • Experience with timing

    analysis for designs at 28nm and below, with a focus on high-speed data

    and signal processing.

  • Proficiency

    in STA tools such as Synopsys PrimeTime, Cadence Tempus, or

    similar.

  • Solid understanding of

    CMOS technology, standard cell libraries, and PVT variations, with a focus

    on high-performance networking and audio applications.

  • Strong scripting skills

    (e.g., TCL, Perl, Python) for automation of STA processes.

  • Ability to work in a

    collaborative environment, with excellent communication and

    problem-solving skills.

  • Experience with timing

    analysis for high-speed networking interfaces (e.g., Ethernet, Wi-Fi) or

    audio processing circuits (e.g., DACs, ADCs).

  • Familiarity with

    low-power design techniques and their impact on timing.

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