Senior ASIC Modeling Software Engineer

Position Overview

About the Role: We're building the simulation platform for UpscaleAI's next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You'll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers' demanding AI infrastructure workloads.

What You'll Work On:

• ASIC Architectural Model: Our current-generation ASIC simulator

• Next-gen ASIC models: Future silicon with enhanced AI networking features

• Multi-chip simulation: Modeling systems with multiple interconnected ASICs

• Performance optimization: Making large-scale simulations practical

Key Responsibilities

• Design and implement software model components that accurately simulate ASIC behavior (forwarding engines, schedulers, memory subsystems, control plane interfaces)

• Translate architectural specifications and microarchitecture documents into high-fidelity C++ models, ranging from functionally accurate to performance-accurate depending on the subsystem

• Develop and maintain the register model, memory map, and configuration interfaces

• Implement packet processing pipelines for multiple forwarding modes

• Optimize model performance for large-scale simulations

• Collaborate with RTL engineers to ensure model-to-silicon correlation

• Work with the architecture team to validate algorithm and architectural choices through simulation

• Work with SDK and platform software teams to enable software development and validation on the model

• Support multiple ASIC versions with maintainable, configurable model architecture

Requirements

• 7+ years of experience in C/C++ architecture model development, cycle-aware simulation, or ASIC verification

• Expert-level C++ programming (modern C++17)

• Deep understanding of network switch/router architecture: forwarding tables, scheduling, QoS, ACLs

• Experience with packet processing pipelines and dataplane simulation

• Familiarity with hardware description languages (Verilog/SystemVerilog) and reading RTL

• Experience with gRPC, Protocol Buffers, or similar IPC mechanisms

• Experience with C++ unit testing frameworks (e.g., Google Test)

• Familiarity with Python for test automation, tooling, and scripting

• Strong debugging skills across software and hardware domains

Nice to Have

• Experience with AI/ML networking (scale-up fabrics, RDMA, collective operations)

• Experience using ns-3 and/or HTSim to model high performance network architectures.

• Familiarity with SAI (Switch Abstraction Interface) or SONiC

• Experience with FPGA prototyping or emulation platforms

• Background in memory subsystem modeling (DDR, HBM, caches)

• Experience with configuration-driven simulation frameworks (YAML, JSON, protobuf-based config)