RTL Engineer Memory Subsystem

Role Overview

We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip.

In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP and PHY partners to transform innovative architectural concepts into production silicon. You will own significant portions of the memory subsystem design, contribute to microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems.

Physical AI workloads are memory-bound: bandwidth, latency, and power in the memory path directly gate what the chip can do. If pushing modern memory technologies to their limits at high speed and low power is the kind of problem you want to own, this role is for you.