FE RTL Designer / SoC integration
Confirmed on the employer's own hiring board on Sep 26, 2026. First seen by Alion on Sep 15, 2026.
About Us: AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.
Why Now: After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.
About the role:
We are looking for a Front-End RTL Designer to contribute to building our Vertical Compute's 3D-integrated chiplets. In this role, you will focus on top-level integration and integrating all IPs to build the AI accelerator that will demonstrate the full potential of our Vertical Integrated Memory (VIM™) technology. You will handle full SoC integration, working in close collaboration with verification and physical design teams to ensure the targeted Power, Performance, and Area (PPA) of the product.
Key Responsibilities:
Lead top-level SoC and chiplet integration, incorporating all internal and third-party IPs to build high-performance AI accelerators.
Integrate proprietary Vertical Integrated Memory (VIM™) technology with compute engines to maximize throughput and bandwidth efficiency.
Partner closely with functional verification teams to build verification environments, debug RTL issues, and ensure robust design coverage.
Collaborate with physical design teams to optimize Power, Performance, and Area (PPA), supporting synthesis, timing closure, and floorplanning.
About the team:
This role is part of the Hardware (HW) team, reporting directly to the HW Manager. You will join a collaborative and innovative team dedicated to delivering cutting-edge AI accelerator solutions and pushing the boundaries of memory and compute integration.
Requirements
About who you are:
Solid background and experience in front-end RTL design and top-level SoC/chiplet integration.
Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
Strong hard skills in RTL languages (SystemVerilog/Verilog), IP integration, and working closely with verification and physical design teams to optimize PPA (Power, Performance, Area).
Strong communication and collaborative problem-solving skills in a fast-paced environment.
Fluency in English with effective written and verbal communication skills.