DFT Engineer - MBIST/GLS
First seen by Alion on Oct 28, 2026.
Job Summary :
- We are looking for a highly skilled and motivated DFT Engineer with strong experience in scan insertion, ATPG, MBIST, GLS, and DFT verification flows.
- The candidate will be responsible for defining and implementing robust DFT architectures and ensuring high test coverage for complex SoC/ASIC designs.
- The ideal candidate should have hands-on industry experience in DFT implementation and validation, with exposure to advanced process nodes and industry-standard EDA tools.
Key Responsibilities :
- Define and implement DFT architecture for SoC / ASIC designs
- Perform scan insertion and scan chain stitching
- Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults
- Implement and verify MBIST / memory repair solutions
- Perform DFT rule checks (DRC) and resolve violations
- Support JTAG / boundary scan / IEEE 1149.1 implementation
- Run and debug Gate Level Simulations (GLS) for DFT patterns
- Analyze and improve test coverage, pattern count, and test time
- Work closely with design, verification, physical design, and silicon validation teams
- Support post-silicon bring-up and failure analysis
- Create DFT documentation, methodology, and best-practice flows
Skills
DFT, MBIST, GLS, ASIC, SoC, Verification, ATPG, Physical Design