Senior ASIC Verification Engineer

Role Overview :

We are looking for an experienced ASIC Verification Engineer with strong hands-on experience in RTL front-end verification at IP, Block, or Subsystem level. The ideal candidate should have strong expertise in SystemVerilog, UVM, and protocol verification, with preferably strong PCIe verification experience.

Mandatory Skills & Experience :

- Minimum 5 years of experience in IP, Block, or Subsystem-level RTL Front-end Verification.

- Minimum 4 years of hands-on experience in SystemVerilog (SV) and UVM-based verification.

- Minimum 2 years of experience with AXI/AHB interfaces.

- Minimum 2 years of experience with PCIe and/or NVMe protocol verification.

- Strong debugging and problem-solving skills.

- Good understanding of ASIC simulation tools and advanced verification methodologies.

- Good communication and collaboration skills.

Good to Have :

- Strong hands-on PCIe verification experience.

- Experience with NVMe verification.

- Scripting experience using Perl and/or Python.

- Experience working on complex ASIC/SoC verification environments.

- Knowledge of advanced verification techniques and methodologies.

Key Responsibilities :

- Develop and execute verification plans for IP, Block, and Subsystem-level RTL designs.

- Develop, maintain, and debug SystemVerilog/UVM-based verification environments.

- Create and execute test scenarios, test cases, and regression suites.

- Verify AXI/AHB interfaces and PCIe/NVMe protocols.

- Perform functional verification, debugging, failure analysis, and root-cause analysis.

- Analyze simulation results and identify RTL/design issues.

- Collaborate with RTL designers and other verification teams to resolve issues.

- Support regression execution and improve verification coverage.

- Apply advanced ASIC verification methodologies to ensure design quality.

Skills

ASIC, RTL, RTL Design, Design Verification, PCI-e, NVMe, UVM, Verilog, System Verilog