Principal Engineer - Verification

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Experience: 10+ yrs

Location: Bengaluru

We are seeking an experienced SoC Verification Technical Lead to lead full-chip System-on-Chip (SoC) verification and drive technical delivery across multiple verification projects or customer engagements. The ideal candidate will have strong expertise in pre-silicon verification, a proven track record of successful SoC tapeouts, and the ability to guide engineering teams toward high-quality verification sign-off.

This role requires a combination of deep technical knowledge, verification methodology development, customer engagement, and engineering leadership to ensure functional correctness, coverage completeness, and predictable project delivery.

Requirements

Key Responsibilities

• Own full-chip SoC verification from test-plan development and execution to coverage closure and final sign-off.
• Verify critical SoC functionality, including boot flows, interconnects, memory subsystems, coherency, interrupts, and clock and reset sequencing.
• Lead multiple verification projects or a major customer account, ensuring technical quality, schedule adherence, and delivery commitments.
• Provide technical leadership to 6-10 engineers through sub-leads, ensuring effective task allocation, technical guidance, and issue resolution.
• Define and standardise reusable verification methodologies, including testbench templates, Verification IP (VIP) strategies, regression infrastructure, and coverage workflows.
• Determine the appropriate distribution of verification activities across simulation, formal verification, emulation, and FPGA prototyping, coordinating with specialist teams.
• Establish and enforce sign-off criteria for functional coverage, code coverage, toggle coverage, assertions, and Gate-Level Simulation (GLS).
• Lead technical reviews, customer discussions, and escalations, communicating verification status, risks, and mitigation plans.
• Support post-silicon debugging by reproducing silicon issues in pre-silicon verification environments and identifying root causes.
• Contribute to effort estimation, project scoping, technical proposals, and Statements of Work (SOW).
• Mentor engineers and sub-leads, develop technical training materials, and participate in technical interviews.
• Improve verification productivity through automation, regression optimisation, reusable components, and AI-assisted verification flows.

What Makes You a Great Fit

• 10-11 years of experience in semiconductor design verification, with strong expertise in full-chip SoC verification.
• At least three successful tapeouts, including a minimum of one full-chip SoC tapeout.
• Proven technical leadership experience managing or guiding teams of six or more engineers.
• Strong understanding of SoC architecture, verification planning, testbench development, coverage closure, and sign-off processes.
• Experience verifying boot flows, interconnects, memory subsystems, coherency, interrupts, and clock/reset sequencing.
• Expertise in reusable verification methodologies, VIP integration, regression management, and coverage analysis.
• Understanding of simulation, formal verification, emulation, FPGA prototyping, and GLS workflows.
• Ability to define verification quality gates, assess technical risks, and drive closure of complex verification issues.
• Strong customer-facing communication, technical presentation, and stakeholder management skills.
• Experience with project estimation, scope definition, technical mentoring, and cross-functional collaboration.
• A continuous-improvement mindset, with interest in automation and AI-assisted verification to improve efficiency and quality.