DFT SENIOR ARCHITECT L3
Confirmed on the employer's own hiring board on Oct 29, 2026. First seen by Alion on Oct 29, 2026.
DFT Senior Architect
Role Purpose
The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction.
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JOB DESCRIPTION
DFT Senior Architect
The Role
Define DFT architecture and test strategy for complex SoCs, and own scan, MBIST, ATPG and pattern delivery from design through silicon bring-up.
- Define DFT architecture and test strategy: scan, compression, MBIST/LBIST, JTAG/IJTAG, boundary scan.
- Plan and implement hierarchical DFT for full-chip and block-level designs.
- Own ATPG, fault-coverage targets, and pattern verification (zero-delay and SDF).
- Resolve DFT DRC and timing issues with RTL and PD teams.
- Deliver patterns to test engineering (STIL / WGL / Verilog) and support ATE bring-up and debug.
- Mentor DFT engineers; support yield analysis and silicon failure diagnosis.
- 15+ years in DFT with multiple SoC tape-outs and silicon bring-up.
- Expert in scan, ATPG, MBIST, at-speed test and hierarchical DFT methodologies.
- Hands-on with Synopsys (DFTMAX / TestMAX), Siemens Tessent or Cadence Modus flows.
- Strong with IEEE 1149.1, 1500 and 1687 standards.
- Working knowledge of STA, synthesis and ATE test flows.
- Scripting in TCl, Python or Perl.
Work Location - Bangaluru, Hyderabad, Pune, Chennai and Kochi
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Deliver
No.
Performance Parameter
Measure
1.
Product design, engineering and implementation
CSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards
2.
Capability development
% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs)
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Mandatory Skills: VLSI Design For Testability - DFT.Experience: >10 YEARS
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