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≈ $104k – $236k per year (Estimated)
Location
Hybrid (Home, United States)
Employment
Full-Time

Confirmed on the employer's own hiring board on Sep 24, 2026. First seen by Alion on Sep 24, 2026. Wolfspeed scores B on the Alion truth index.

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Wolfspeed manufactures silicon carbide materials and power semiconductors. Its devices improve efficiency in electric vehicles, industrial drives and renewable energy systems. The company operates large domestic wafer and device fabrication plants.

As an Applications Engineer for Advanced Packaging, you will provide pre- and post-sales technical support to customers integrating Wolfspeed SiC substrates into 2.5D and 3D packaging architectures for high-performance computing (HPC) and AI data center applications. Building on Wolfspeed's 35+ years of SiC materials leadership and an established portfolio of proven use cases, you will act as the technical bridge between our materials expertise and the customer's package design - showing customers exactly where and why SiC delivers value across heat spreaders and carriers, passive and active interposers, and package substrates. Beyond supporting today's use cases, you are expected to generate your own ideas for new SiC applications and to engage closely with partners, customers, and foundries to co-design next-generation architectures. With a defined product roadmap and active foundry, OSAT, and hyperscaler engagements already underway, you will guide customers with authority through use-case identification, material selection, design validation, and qualification. The ideal candidate brings a strong technical foundation in semiconductor packaging, thermal simulation, and process integration.

Key responsibilities:

  • Guide customer packaging engineers, foundries, and OSATs in selecting the optimal SiC use case (heat spreader, carrier, passive/active interposer, or package substrate) and incorporating Wolfspeed SiC wafers and substrates into advanced packaging architectures (2.5D/3D heterogeneous integration, CoWoS-style platforms). Provide remote and on-site technical support.
  • Proactively identify and propose new SiC use cases, and partner closely with customers, foundries, OSATs, and ecosystem players to co-design novel packaging architectures that extend SiC beyond today's applications.
  • Lead the design, development, and documentation of reference demonstrations for SiC interposer, heat-spreader, and substrate applications, including thermal performance benchmarks that quantify SiC's operating-temperature, hot-spot, and thermal-cross-talk advantages over silicon, glass, and ceramic.
  • Supply customers with validated SiC material characteristics - including anisotropic/directional thermal conductivity and bond-interface data - to drive accurate package-level thermal modeling.
  • Develop and present technical materials at packaging industry conferences and tradeshows and ecosystem partner workshops.
  • Support new product and PDK launches, including training for Wolfspeed sales teams, foundry partners, and EDA ecosystem players (e.g., Cadence, Synopsys) on SiC design rules, process windows, and integration guidelines.
  • Provide product managers with consolidated customer requirements and use-case prioritization to define new SiC packaging products, interposer specifications, and PDK enhancements.

Qualifications:

  • Bachelor's Degree in Electrical Engineering, Materials Science, or equivalent with relevant experience.
  • Deep industry know-how- an insider's understanding of how hyperscalers, foundries, and OSATs specify advanced packages, and the ability to translate their thermal, power-density, warpage, cost, and reliability requirements into SiC material and product specifications.
  • Understanding of advanced packaging architectures including 2.5D/3D integration, interposer structures, TSV/TSiCV fabrication, and chiplet design.
  • Experience with thermal simulation tools (e.g., ANSYS Icepak, FloTHERM) for package-level thermal analysis; ability to model and communicate SiC's thermal advantages in high-power-density scenarios (AI chips approaching 250+ W/cm² by 2030).
  • Familiarity with packaging process flows: wafer thinning, via etching (RIE), metallization, micro-bump/hybrid bonding, and CTE mismatch considerations for SiC integration.
  • Experience with EDA or simulation environments relevant to packaging (e.g., Cadence Sigrity, Synopsys) is a plus.
  • Strong oral and written communication and presentation skills.

The ideal candidate will be located at ourheadquarter in Durham, North Carolina.

We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, national origin, disability status, protected veteran status, or any other characteristic protected by law.

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