Dayton Harvey
Hardware
MATLAB
Python
C++
Verilog
C
Active 14 days ago
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Overview
Technical skills
Timeline
Roles
Overview
Master of Engineering graduate in Electrical Engineering and Computer Science with a specialization in digital signal processing and high-speed data systems. Hands-on experience with MATLAB and Python modeling, Verilog RTL verification and co-validation, and spectral/performance analysis for DSP and embedded/mixed-signal workflows. Built FPGA and embedded systems and developed system-level validation and DSP pipeline designs.
Technical skills
MATLAB
Python
C++
Verilog
C
AI/ML
AI Agents
CNN
DevOps
AWS
Git
Chips/EDA
Cadence Spectre
Cadence Xcelium
Siemens ModelSim
Timeline
University of California (Irvine Campus)
Master's Degree •
Electrical Engineering and Computer Science
Team lead and System Engineer for the project. We developed behavioral models for a time-interleaved 2 level hierarchical 64-channel SAR ADCs with an aggregate speed of 100GS/s using AI agents to assist in creation of both behavioral python and emulatable Verilog RTL implementation.
Python
Verilog
University of California (Davis Campus)
Bachelor's Degree •
Computer Engineering