Overview
Technical skills
Projects
Timeline
Roles

Overview

Master of Engineering graduate in Electrical Engineering and Computer Science with a specialization in digital signal processing and high-speed data systems. Hands-on experience with MATLAB and Python modeling, Verilog RTL verification and co-validation, and spectral/performance analysis for DSP and embedded/mixed-signal workflows. Built FPGA and embedded systems and developed system-level validation and DSP pipeline designs.
Phone

Technical skills

Python
C++
Verilog
C
MATLAB
Chips/EDA
Cadence Spectre
Cadence Xcelium
Siemens ModelSim
DevOps
AWS
Git
AI/ML
AI Agents
CNN

Projects

Jan 2026 to Jun 2026 5 Months

Team lead and System Engineer for the project. We developed behavioral models for a time-interleaved 2 level hierarchical 64-channel SAR ADCs with an aggregate speed of 100GS/s using AI agents to assist in creation of both behavioral python and emulatable Verilog RTL implementation.

Python
Verilog

Timeline

University of California (Irvine Campus)
Master's Degree • Electrical Engineering and Computer Science
2025–2026 Irvine, California
University of California (Davis Campus)
Bachelor's Degree • Computer Engineering
2019–2024 Davis, California