Shravani Singavarapu

Designed multilayer high-speed PCBs, including DDR3/DDR4 memory interfaces and mixed-signal layouts, with emphasis on signal integrity, grounding strategy, and overall reliability. Used Cadence Allegro and OrCAD to set electrical constraints, perform placement and routing, and validate rules via DRC. Worked on impedance-controlled and differential routing and implemented via technologies including HDI structures and back drilling. Also contributed to project planning, knowledge sharing with trainees, and team coordination for customer deliverables.

Created a high-density 12-layer I/O controller PCB for mission-critical high-speed data acquisition and control. Integrated DDR3 memory at 800 Mbps, 1G Ethernet, flash storage, and ADC inputs while addressing mixed analog-digital signal integrity. Focused on routing constraints for DDR3 and Ethernet and supported integration and validation with hardware and firmware teams using Allegro.

Designed a complex 16-layer mixed-signal PCB supporting digital logic and multiple isolated analog ground domains. Coordinated connector placement along a single board edge and ensured careful routing for interfaces such as MIL-STD-1553B, RGMII Ethernet, SPI, I2C, and ADC inputs. Led end-to-end PCB design strategy and collaborated with cross-functional teams for reviews, validation, and customer deliverables using Allegro.

Designed a compact 14-layer PCB for a Zynq UltraScale+ based embedded module with a two-board stack and fine-pitch connectors. Integrated high-speed interfaces including CAMLINK at 595 MHz, 1G Ethernet, ADC/DAC channels, and multiple serial interfaces while addressing signal integrity and grounding. Applied DDR4 memory design and ensured reliable power and routing within a tight timeline using Allegro.