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Financials
Technologies
Tech DNA
SystemVerilog
Verilog
Perl
UVM
Hardware
SystemVerilog
Verilog
C++
SystemC
TCL Scripting
Formal Verification
UVM
Synopsys PrimeTime
Synopsys Verdi
Tessent
Ansys SIwave
Cadence Allegro
Synopsys HSPICE
Cadence Palladium
Cadence Protium
Siemens Veloce
Synopsys ZeBu
Other
Perl
Python
AI Agents
HPC
YouTube
LinkedIn
Zoho CRM
Stack modernity
62/100
How modern this stack is, based on technology relevance, AI adoption and the share of legacy tools.
In-demand technologies
SystemVerilog
10 jobs
Required
Formal Verification
9 jobs
Required
Verilog
8 jobs
Required
Perl
6 jobs
Required
C++
4 jobs
Required
UVM
4 jobs
Required
Python
3 jobs
Required
Synopsys PrimeTime
3 jobs
Required
Salary medians are calculated from this company's open jobs and compared with the market.
Industry adoption
Python
7%
AI Agents
5%
LinkedIn
3%
C++
2%
YouTube
1%
Share of companies in the same industry that use each technology.
Stack changes
TCL Scripting
Sep 2026
SystemC
Sep 2026
Synopsys ZeBu
Sep 2026
Siemens Veloce
Sep 2026
Cadence Protium
Sep 2026
Cadence Palladium
Sep 2026
UVM
Sep 2026
Synopsys Verdi
Sep 2026
Technologies recently added to or removed from this company's stack - a signal of tech migrations and new initiatives.
Salary insights
Compensation ranges based on this company's open jobs
Median
$280k
Typical range
$270k – $290k
Open positions
2
2
Jobs
Senior
100%
| Level | Jobs | Median | Typical range |
|---|---|---|---|
| Senior | 2 | $280k | $270k – $290k |
Highest paying role
Sales Manager/Sr. Sales Manager – Industrial Product Eng. Services (East Coast - US)
$290k
Normalized to USD per year
Growth
Hiring Momentum
28/100
Slowing
Open positions
32
0 opened / 0 closed in 30 days
Hiring Focus
The percentage next to each role is its share of the company's job openings over the last 90 days; the arrow shows the shift versus the previous period.
Industrial Engineering
43% ▲
Sales
29% ▲
Hardware
14% ▲
HR
14% ▲
Offices
Where the company hires and what each office is for
Cities
5
Hiring now
5
Countries
3
Busiest office
Bengaluru
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Headquarters
Builds here
Office with open vacancies
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Bengaluru
India
Regional office
12 open roles 58% engineering 200-500 est. staff
hires for Hardware, Industrial Engineering, Sales
Hyderabad
India
Plant / site
9 open roles 2 posted in 90 days 200-500 est. staff
hires for Industrial Engineering, HR
Hyderabad
Pakistan
Plant / site
7 open roles 2 posted in 90 days 43% engineering 50-200 est. staff
hires for Industrial Engineering, Hardware
Santa Clara
United States
Regional office
3 open roles 2 posted in 90 days 33% engineering 50-200 est. staff $270k Avg Salary
hires for Hardware, Sales, Industrial Engineering
Texas City
United States
1 open roles 1 posted in 90 days 10-50 est. staff $290k Avg Salary
hires for Sales
Jobs
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≈ $38k – $90k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
SystemVerilog
Formal Verification
Apply
≈ $38k – $90k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
SystemVerilog
Formal Verification
Apply
≈ $29k – $76k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
SystemVerilog
Formal Verification
Apply
≈ $35k – $75k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
SystemVerilog
Formal Verification
Apply
≈ $147k – $283k per year (Estimated) • In office • Full-Time • 10+ years exp • Santa Clara
Python
SystemVerilog
Perl
Formal Verification
Apply
≈ $38k – $90k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
C++
SystemVerilog
Perl
UVM
Formal Verification
Synopsys Verdi
Apply
≈ $29k – $76k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
C++
SystemVerilog
Perl
UVM
Formal Verification
Synopsys Verdi
Apply
≈ $35k – $75k per year (Estimated) • In office • Full-Time • Bengaluru
Verilog
C++
SystemVerilog
Perl
UVM
Formal Verification
Synopsys Verdi
Apply
≈ $40k – $103k per year (Estimated) • In office • Full-Time • Hyderabad
Verilog
SystemVerilog
Formal Verification
Apply
≈ $40k – $86k per year (Estimated) • In office • Full-Time • 3+ years exp • Bachelor's Degree • Hyderabad
Python
C++
SystemVerilog
SystemC
TCL Scripting
HPC
Chips/EDA
UVM
Synopsys ZeBu
Cadence Palladium
Siemens Veloce
Cadence Protium
Apply

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