Semiconductor Engineering
semiengineering.com
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Overview
Semiconductor Engineering is an American trade publication founded in 2013 that covers chip design, verification, manufacturing and packaging for an audience of practising engineers and industry executives. It publishes technical articles, interviews with tool and foundry vendors, and analysis of process nodes, advanced packaging, low-power design and design automation, alongside a knowledge base of reference material on semiconductor topics. The site is run by a small editorial team, funded by sponsorship from equipment and design software companies, and is widely read across the semiconductor supply chain.
News
How Data Center AI Can Keep Growing, Despite Supply Chain Bottlenecks
Efficiency is key for the next two to five years. But what happens when supply eventually catches up?
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Report
Research Bits: Aug. 10
Thin chip stacking; analog CAM with MoS2; sensor-level processing and memory.
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Report
Mathematical Model Explains Bondwave Velocity and its Acceleration in Direct Wafer-Wafer Bonding (imec)
An imec researcher published a technical paper titled
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Report
Scale Up, Scale Out Challenges Amplified For Clusters
Compute clusters offer more processing capacity but at the cost of higher power. Software is needed to allocate resources effectively and optimize networking and memory.
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Report
Humanoid Robots Applications
Solutions supporting every key humanoid robot function, including force and touch sensors, GaN for robotics, MCUs, motor control, battery management systems and power management.
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From Blueprint To Build: Engineering The World's Largest AI Chips
Building hyper-large form factor packages that measure up to 240 mm x 240 mm with reliable encapsulation.
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Chip Industry Week In Review
DAC's big buzz; CHIPS Act $; China's immersion DUV; UMC expands; SIA's state of the industry; DRAM shortages; earnings; PCB design credential program; IBM's quantum advantage; AI security alliance; foreign robotics ban.
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Report
Flat Enough? Warpage Management Gets Harder In Advanced Packaging
As packages get larger and thinner, warpage is becoming a process-control problem rather than a simple flatness spec.
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When semiconductor materials misbehave
The gap between lab performance and fab reality is growing wider as packages grow more complex.
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Foundry Capacity Is Limiting Who Competes at Leading Edge Nodes
But the inability to utilize leading-edge process nodes has created opportunities for small and midsize chip developers in multi-die design, along with some sophisticated architectural design tradeoffs.
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Tech stack
The technologies known for Semiconductor Engineering, by layer.
Languages
Python
C++
Verilog
SystemVerilog
Perl
VHDL
SQL
MATLAB
Frameworks & libraries
UVM
LangChain
PyTorch
PyTorch C++
TensorFlow
CUDA
TensorFlow C++
Cloud & platforms
Azure
Cadence Protium
AWS
GitHub
GCP
Spark
GitHub Actions
Kubernetes
Developer tools
Formal Verification
Cadence Palladium
Cadence Xcelium
Jenkins
Cadence Virtuoso
Copilot
Git
Cadence Conformal
AI & ML
LLM
Claude
Practices & domains
AI Agents
CI/CD
RAG
HPC
SLI/SLO/SLA
Configuration Management
Embeddings
Prompt Engineering
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Products
Industry Newsletters
Email digests summarising design, manufacturing and packaging developments. They carry the sponsorship that funds the publication.
semiengineering.com
Sponsored Technical Papers
A library of vendor-supplied white papers and blogs hosted alongside the editorial. It is one of the site's main revenue sources.
semiengineering.com
Knowledge Centre
A reference library of explainer entries covering semiconductor terms and technologies. It is used as an onboarding resource across the industry.
semiengineering.com
Editorial Coverage
Daily technical articles on chip design, verification, manufacturing and packaging. The reporting targets working engineers rather than general readers.
semiengineering.com
People
Ed Sperling
Editor in Chief
Ed Sperling founded the publication in 2013 after editing several other semiconductor trade titles. He sets the editorial direction and writes much of the analysis.
Names and roles come from public filings, company registers and the company's own site. Is this you? Correct or remove · How we handle this data
Growth
Hiring Momentum
38/100
Slowing
Open positions
0
0 opened / 0 closed in 30 days
Hiring Dynamics
0%
Activity Timeline
Added ETL/ELT to stack
Aug 2026
Added OpenAI Codex to stack
Aug 2026
Added OpenAI to stack
Aug 2026
Added cuDNN to stack
Aug 2026
Added GitLab to stack
Aug 2026
Added Edge AI to stack
Aug 2026
Added Least Privilege to stack
Aug 2026
Added InfiniBand to stack
Aug 2026
Added GPT-5 to stack
Aug 2026
Added GitHub to stack
Aug 2026
Added TGI to stack
Aug 2026
Added Structured Outputs to stack
Aug 2026
Offices
Where the company hires and what each office is for
Cities
1
Hiring now
0
Countries
1
San Jose
United States
HQ