SiFive
sifive.com
Actively hiring
Electronic Components
Semiconductors
Information Technology
Hardware
Embedded Systems
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Financials
Overview
SiFive is an American semiconductor company founded in 2015 by the Berkeley researchers who created the RISC-V instruction set, and it designs processor cores that others license and build into their own chips. Its business is an alternative to Arm: because RISC-V is an open standard rather than a proprietary architecture, customers can extend the instruction set for their own workloads without negotiating with the architecture owner, which has drawn interest from companies building custom artificial intelligence and automotive silicon. Headquartered in Santa Clara, it licenses cores to chipmakers, cloud operators and defence customers rather than manufacturing anything itself.
News
SiFive pushes development server to take RISC-V into the datacenter
Rack-mount system intended for software porting, workload optimization, to bring open standard to the bitbarn
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Report
SiFive brings RISC-V servers with Ubuntu 26.04 and RHEL 10 for code developers
To solve the chicken-and-egg problem for RISC-V in data centers, SiFive is providing developer servers with 32 RVA23 cores, 256 GB RAM, and PCIe 5.0.
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Report
SiFive Drives RISC-V Into The Data Center With BigSky Server Platform
SiFive debuted its BigSky SF-2U870 2U server platform at Hot Chips, delivering 32 P870 RISC-V cores, 256GB DDR5 memory, and enterprise Linux.
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Technologies
Tech DNA
SystemVerilog
Verilog
Python
UVM
CUDA
PyTorch
Hardware
SystemVerilog
Verilog
Chisel
C++
VHDL
UVM
Formal Verification
Synopsys Verdi
Cadence Xcelium
PyTorch C++
OpenOCD
Cadence JasperGold
Synopsys VC Formal
AI/ML
Python
Git
CUDA
CUDA Toolkit
PyTorch
OpenCL
ROCm
TPU
Other
Perl
Java
Haskell
Stack modernity
64/100
How modern this stack is, based on technology relevance, AI adoption and the share of legacy tools.
In-demand technologies
SystemVerilog
55 jobs
Required
$219k
Median
Verilog
39 jobs
Required
$219k
+7% vs market
Python
37 jobs
Required
$194k
+8% vs market
UVM
34 jobs
Required
$223k
+1% vs market
Chisel
31 job
Required
$219k
Median
Scala
29 jobs
Required
$206k
+17% vs market
C++
22 jobs
Required
$219k
+9% vs market
Formal Verification
20 jobs
Required
$283k
+17% vs market
Salary medians are calculated from this company's open jobs and compared with the market.
Industry adoption
Python
24%
Git
16%
Java
13%
C++
10%
PyTorch
7%
Verilog
2%
Share of companies in the same industry that use each technology.
Stack changes
TPU
Sep 2026
ROCm
Sep 2026
PyTorch C++
Sep 2026
PyTorch
Sep 2026
OpenOCD
Sep 2026
OpenCL
Sep 2026
Git
Sep 2026
CUDA Toolkit
Sep 2026
Technologies recently added to or removed from this company's stack - a signal of tech migrations and new initiatives.
SemiWiki
NVIDIA
NXP Semiconductors
Intel Corporation
Qualcomm
Broadcom
Salary insights
Compensation ranges based on this company's open jobs
Median
$219k
Typical range
$171k – $311k
Open positions
17
15
Jobs
Middle
26.7%
Senior
20%
Staff
26.7%
Principal
13.3%
Architect
13.3%
| Level | Jobs | Median | Typical range |
|---|---|---|---|
| Middle | 4 | $206k | $171k – $251k |
| Senior | 3 | $194k | $194k – $219k |
| Staff | 4 | $251k | $219k – $251k |
| Principal | 2 | $283k | $283k |
| Architect | 2 | $297k | $283k – $311k |
Highest paying role
SOC Architect
$311k
Normalized to USD per year
Products
Custom Core Design
Engineering work adapting cores to a specific customer's workload and instruction extensions. This is the capability that a fixed architecture licence cannot offer, and it is the company's clearest argument against the incumbent.
sifive.com
Essential Series
Configurable cores for embedded and general-purpose use across a wide performance range. It is the volume catalogue that gives customers a starting point without commissioning a bespoke engagement, and it is how most new licensees enter.
sifive.com
Automotive Series
Functional safety qualified cores for vehicle applications. Automotive certification takes years and locks a supplier into a platform for its production life, which makes these design wins particularly valuable.
sifive.com
Intelligence Series
Cores with vector processing designed for machine learning workloads at the edge and in data centres. Vector extensions are where RISC-V's ability to be customised matters most, because artificial intelligence workloads change faster than architectures normally do.
sifive.com
Processor Core IP
Licensable RISC-V processor cores ranging from small embedded controllers to high-performance application processors. Customers pay licence fees and per-chip royalties, which means revenue arrives years after the design work is done.
sifive.com
People
Andrew Waterman
Co-founder
Andrew Waterman co-created RISC-V as a graduate student and wrote much of its original specification. He co-founded the company alongside his Berkeley colleagues.
Yunsup Lee
Co-founder
Yunsup Lee co-founded the company after working on the original RISC-V implementations at Berkeley. He has led its processor engineering organisation.
Krste Asanovic
Co-founder and Chief Architect
Krste Asanovic co-created the RISC-V instruction set at Berkeley and co-founded the company to commercialise it. He chairs the RISC-V International board that governs the standard.
Growth
Hiring Momentum
60/100
Growing
Open positions
87
11 opened / 3 closed in 30 days
Median time-to-fill
58 days
faster than 27% of the market
ATS activity
Every ~3 hours
Today
Hiring Dynamics
+100%
Hiring Focus
The percentage next to each role is its share of the company's job openings over the last 90 days; the arrow shows the shift versus the previous period.
Hardware
70% ▼
DevOps
18% ▲
Backend
5% ▲
QA
4% ▼
Frontend
2% ▼
Product
2% ▲
Actively hiring for Hardware (+16 in 30 days)
Activity Timeline
+11 jobs in a week
Sep 2026
Added TPU to stack
Sep 2026
Added ROCm to stack
Sep 2026
Added PyTorch C++ to stack
Sep 2026
Added PyTorch to stack
Sep 2026
Added OpenOCD to stack
Sep 2026
Added OpenCL to stack
Sep 2026
Added Git to stack
Sep 2026
Added CUDA Toolkit to stack
Sep 2026
Added CUDA to stack
Sep 2026
Added Java to stack
Sep 2026
Added Haskell to stack
Sep 2026
Jobs
In office • Full-Time • 8+ years exp • Bachelor's Degree • Hsinchu
C++
PyTorch C++
AI/ML
CUDA
CUDA Toolkit
OpenCL
PyTorch
ROCm
TPU
DevOps
Git
Chips/EDA
OpenOCD
Apply
≈ $20k – $46k per year (Estimated) • In office • Full-Time • 1+ year exp • Bachelor's Degree • Bengaluru
C++
Haskell
Java
Perl
Python
SystemVerilog
Verilog
VHDL
UVM
Apply
≈ $23k – $56k per year (Estimated) • In office • Full-Time • Bachelor's Degree • Bengaluru
C++
Perl
Python
SystemVerilog
Verilog
Apply
≈ $37k – $76k per year (Estimated) • In office • Full-Time • 6+ years exp • Hyderabad
SystemVerilog
Verilog
UVM
Apply
≈ $40k – $81k per year (Estimated) • In office • Full-Time • 8+ years exp • Bachelor's Degree • Bengaluru
Chisel
SystemVerilog
Verilog
VHDL
Cadence JasperGold
Formal Verification
Synopsys VC Formal
Apply
≈ $38k – $77k per year (Estimated) • In office • Full-Time • 8+ years exp • Bachelor's Degree • Hyderabad
SystemVerilog
Cadence Xcelium
Synopsys Verdi
UVM
Apply
≈ $26k – $62k per year (Estimated) • In office • Full-Time • 5+ years exp • Bachelor's Degree • Hyderabad
SystemVerilog
Verilog
Cadence Xcelium
Synopsys Verdi
UVM
Apply
≈ $37k – $76k per year (Estimated) • In office • Full-Time • 10+ years exp • Bachelor's Degree • Hyderabad
SystemVerilog
Verilog
Cadence Xcelium
Formal Verification
Synopsys Verdi
UVM
Apply
≈ $26k – $62k per year (Estimated) • In office • Full-Time • 5+ years exp • Bachelor's Degree • Hyderabad
SystemVerilog
Verilog
Cadence Xcelium
Synopsys Verdi
UVM
Apply
≈ $37k – $76k per year (Estimated) • In office • Full-Time • 8+ years exp • Bachelor's Degree • Hyderabad
SystemVerilog
Verilog
Formal Verification
UVM
Apply
≈ $26k – $62k per year (Estimated) • In office • Full-Time • Hyderabad
SystemVerilog
Verilog
UVM
Apply
$206k – $251k per year • In office • Full-Time • 8+ years exp • Master's Degree • Santa Clara • Hsinchu • Austin • Bengaluru
Apply
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