FPGA SW Validation Engineer (PR)

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Job Description:

Job Description

1. Validates and researches the Compiler optimizations, Partial Reconfiguration (PR) flow, Debuging features like SignalTap & System Console, etc. using Quartus Design Software and Altera FPGA Hardware.

2. Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA Hardware Boards.

3. Regresses the designs during each release for QoR, and monitors performance over the targeted FPGA devkits to assess improvements.

4. Collaborates with cross-functional teams to develop and improve validation strategies for improving Compiler/PR validation and help resolve customer issues as they occur.

Qualifications:

Qualifications:

Experience : Min. 6+ years of relevant experience in FPGA/ASIC Design, RTL Coding, Verification and HW Debug

Education : Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines

Requirements -

1. FPGA/Digital Logic Design, RTL/HDL design and verification using VHDL, Verilog or SystemVerilog.

2. Experienced in FPGA Devices like Agilex, Virtex and Tools like Altera Quartus, Xilinx Vivado, Synplify, etc

3. Good experience in FPGA Partial Reconfiguration (PR) flow, and Hardware design and debugging using SignalTap or ChipScope

4. Good experience with Simulation/Verification of digital designs using QuestaSim, VCS, XCelium, STA and Hardware validation of FPGA Designs

5. Knowledge of Unix/Linux along with Automation, like Shell, Perl/TCL or Python Scripting is required

6. Knowledge of PCIe, Ethernet, Avalon bus protocols, AHB, AXI, HPS and High-Speed interfaces are essential

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