Product Physical Failure Analysis Engineer
Confirmed on the employer's own hiring board on Nov 9, 2026. First seen by Alion on Aug 21, 2026. Altera scores A on the Alion truth index.
Job Details:
Job Description:
About Altera
At Altera™, our independence as the world’s largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
We are seeking an experienced semiconductor Physical Failure Analysis Engineer responsible for root cause identification on yield, reliability and customer returns. Drives failure identification in processes and products and searches for improvements to enhance yield, performance, quality, and reliability of next generation product and package technologies. Collaborates with design and process development engineers to determine relationship of materials properties and electrical performance and thoroughly explains fundamental aspects of material and device interactions as needed to assist in the transfer new product to manufacturing. Adds to the development of electrical, analytical, and mechanical methodologies by developing failure mode and effects analysis (FMEA) and maintaining control plans throughout the product lifecycle. Applies strategic failure analysis capabilities for future technologies and products, drives automation and improvement of failure analysis process, and conducts innovative use of new analytical tools, equipment, and methodologies. Develops, records, and performs failure analysis on systems and components to identify root cause, analyze failure reports, and recommend corrective action to prevent reoccurrence of problems.
Key Responsibilities
Collaborate with Product/Yield/Reliability Engineers to drive fault isolation during product development, yield improvement and reliability risk assessments
Support physical failure analysis and root cause determination of semiconductor device failures
Collaborate with Fault isolation engineers or Independently interpret Emission microscopes, Laser Voltage Probing and OBIRCH data and to define physical failure analysis process
Independently define, and execute physical failure analysis tools such as SEM, FIB and EDX
Experienced with layout, schematic and design analysis tools
Develop reports and communicate findings to the responsible engineers on a regular basis
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $215,925 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications
BS degree in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, or a related field
8+ years of experience in semiconductor failure analysis
8+ years of experience with Layout & Design tools (Virtuoso, Avalon, SysNav, etc.)
8+ years of experience independently implementing failure analysis using die milling/thinning, Focused Ion Beam milling for layer-by-layer deprocessing of silicon die, Scanning Electron Microscopy, and Energy Dispersive X-ray Spectroscopy
8+ years of experience driving investigations to root cause and driving yield/reliability improvements
Preferred Qualifications
Understanding of FPGA architecture
Understanding design debug features (DFT)
Experience with using Teradyne Ultraflex tester
Experience in semiconductor packaging failure analysis.