Junior SI/PI and Packaging Engineer

Annapurna Labs is the team behind AWS Graviton the industry's most advanced ARM-based server SoC.

We operate like a start-up with the scale of the world's largest cloud provider.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.

What sets us apart:

• Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
• Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
• Holistic view of the entire interconnect, from the DIE’s metals, through the Package, to the PCB traces, and all the way to the peer device.
• In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
• Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces. The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Lab’s Chip development team. The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives. The team’s work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGA’s substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes. We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain. Key job responsibilities
• Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
• End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
• Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

Basic qualifications

- BSc in Electrical Engineering or in related field

- Background in board design, or lab measurement of digital high-speed interfaces.

- Familiarity with Signal and Power integrity simulation tools.

Preferred qualifications

- Familiarity with high-speed digital interfaces such as DRAM/PCIe/SerDes.

- Previous experience with lab equipment (e.g oscilloscope, spectrum analyzer)

- Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice)

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