Technical Leader Physical Design
Confirmed on the employer's own hiring board on Oct 18, 2026. First seen by Alion on Aug 10, 2026. Amazon scores A on the Alion truth index.
Annapurna Labs, an Amazon team, designs and delivers high-end, custom silicon at the heart of AWS. Our chips don't just support the cloud - they define it. From Trainium, the purpose-built ML accelerator driving the next wave of AI innovation, to Graviton, the Arm-based server processor redefining price-performance for compute workloads, to Nitro, the advanced network and cloud management controller that underpins every AWS instance - Annapurna's products set the standard for the industry.
Founded by industry veterans and operating as a fabless semiconductor company within AWS, Annapurna Labs combines the agility of a startup with the scale of the world's largest cloud provider. Our engineers work with cutting-edge technologies to innovate and shape the future of cloud computing- designing the leading-edge semiconductor products that power Amazon's infrastructure. Here, you'll experience a fast-paced environment with continuous learning opportunities and the chance to develop next-generation platforms.
Exciting opportunity to join Amazon in developing its next generation products for the cloud market.
We are looking for talented people to join us, as leaders in our excellent Physical Design team, adopting super advanced process nodes, mentoring team members, and further developing our implementation methodologies.
Watch these videos to learn more about Annapurna Labs:
AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0
AWS re:Invent 2025 - Deep Dive into the AWS Nitro System https://www.youtube.com/watch?v=cD1mNQ9YbeA
AWS re:Invent 2025 - AWS Graviton https://www.youtube.com/watch?v=haSHl2BLhm8
Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.
A day in the life
Your day will be a dynamic blend of technical innovation and collaborative problem-solving. You'll dive deep into intricate chip design processes, working with state-of-the-art tools and technologies to create semiconductor solutions that drive cloud computing forward. Expect to engage in complex design challenges, collaborate with brilliant engineers, and see your work directly impact global technological advancement.
About the team
We are a passionate group of semiconductor experts dedicated to pushing the boundaries of cloud technology. Our team thrives on innovation, collaboration, and continuous learning. We value diverse perspectives and believe that breakthrough technologies emerge from inclusive, supportive environments where every team member can contribute their unique insights.
Basic qualifications
- 8+ years of experience in physical design
- Understanding the entire place and route flow (“RTL to GDS”)
- Very deep understanding of timing
- Process and technology (advanced nodes) oriented
- Leadership and mentoring skills
Preferred qualifications
- Full-chip experience (floor plan, layout, timing)
- Previous experience in high-speed designs, multi-voltage (low power) designs
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