DFT/DFx Architecture & RTL Lead

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THE ROLE:

The Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.

In this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.

Be part of a collaborative team delivering advanced IP used across SoCs.

THE PERSON:

The successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.

KEY RESPONSIBILITIES:

• Define and lead PHY-specific DFT/DFx architecture and methodology for high-speed SerDes, Memory PHY, and die-to-die interconnect IPs.
• Implement DFT/DFx features in RTL using Verilog/SystemVerilog.
• Develop and support DFT micro-architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features.
• Support JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.
• Support Siemens Tessent-based or equivalent industry-standard DFT flows for ATPG, pattern generation, pattern validation, and debug.
• Support scan stitching, scan-readiness checks, test coverage analysis, and DFT rule/debug closure.
• Develop and maintain DFT timing constraints, test-mode constraints, and integration guidelines compatible with front-end and physical design flows.
• Perform gate-level simulation and debug using tools such as Synopsys VCS and Verdi or comparable tools.
• Drive SpyGlass or equivalent lint/DFT-readiness analysis to identify scan, controllability, observability, and test coverage gaps.
• Plan, implement, and verify MBIST-related features for embedded memories.
• Support ATPG pattern generation, simulation, debug, and delivery to test engineering.
• Partner with Test Engineering and Product Engineering on silicon bring-up, tester pattern debug, diagnosis, and yield-learning activities.
• Develop efficient and reusable DFx flows, scripts, checkers, and methodologies for IP-level and SoC-level integration.

PREFERRED EXPERIENCE:

• Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on demonstrated technical scope, relevant experience, and role-related interview criteria.
• Understanding of DFT architecture and micro-architectures, including scan, compression, test clocks, test resets, lock-up latches, clock gates, scan anchors, and test access mechanisms.
• Hands-on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent TestKompress, Tessent MemoryBIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN, or experience with comparable industry-standard DFT tools and methodologies.
• Experience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs.
• Hands-on RTL coding experience in Verilog and/or SystemVerilog.
• Experience with industry-standard ATPG, scan insertion, and DFT implementation tools.
• Familiarity with JTAG, IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT concepts.
• Experience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies.
• Experience analyzing DFT readiness, lint, controllability, observability, and test coverage issues.
• Understanding of MBIST planning, implementation, verification, and debug.
• Understanding of low-power design concepts such as power gating, multi-voltage domains, multi-Vt usage, isolation, retention, and voltage scaling.
• Understanding of high-performance and low-power digital design fundamentals.
• Knowledge of common fault models, including stuck-at, transition, path delay, gate-exhaustive, IDDQ, and cell-aware fault models.
• Demonstrated ability to investigate and resolve issues across RTL, gate-level netlists, constraints, patterns, and silicon behavior.
• Ability to communicate technical information effectively and collaborate across design, verification, CAD, physical design, and test engineering teams.
• Candidates are encouraged to apply even if their experience does not include every tool or technology listed above. Experience with comparable tools, methodologies, and technically relevant environments may also be considered.

ACADEMIC CREDENTIALS:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant technical education and industry experience where appropriate.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

The Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.

In this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.

Be part of a collaborative team delivering advanced IP used across SoCs.

THE PERSON:

The successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.

KEY RESPONSIBILITIES:

• Define and lead PHY-specific DFT/DFx architecture and methodology for high-speed SerDes, Memory PHY, and die-to-die interconnect IPs.
• Implement DFT/DFx features in RTL using Verilog/SystemVerilog.
• Develop and support DFT micro-architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features.
• Support JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.
• Support Siemens Tessent-based or equivalent industry-standard DFT flows for ATPG, pattern generation, pattern validation, and debug.
• Support scan stitching, scan-readiness checks, test coverage analysis, and DFT rule/debug closure.
• Develop and maintain DFT timing constraints, test-mode constraints, and integration guidelines compatible with front-end and physical design flows.
• Perform gate-level simulation and debug using tools such as Synopsys VCS and Verdi or comparable tools.
• Drive SpyGlass or equivalent lint/DFT-readiness analysis to identify scan, controllability, observability, and test coverage gaps.
• Plan, implement, and verify MBIST-related features for embedded memories.
• Support ATPG pattern generation, simulation, debug, and delivery to test engineering.
• Partner with Test Engineering and Product Engineering on silicon bring-up, tester pattern debug, diagnosis, and yield-learning activities.
• Develop efficient and reusable DFx flows, scripts, checkers, and methodologies for IP-level and SoC-level integration.

PREFERRED EXPERIENCE:

• Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on demonstrated technical scope, relevant experience, and role-related interview criteria.
• Understanding of DFT architecture and micro-architectures, including scan, compression, test clocks, test resets, lock-up latches, clock gates, scan anchors, and test access mechanisms.
• Hands-on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent TestKompress, Tessent MemoryBIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN, or experience with comparable industry-standard DFT tools and methodologies.
• Experience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs.
• Hands-on RTL coding experience in Verilog and/or SystemVerilog.
• Experience with industry-standard ATPG, scan insertion, and DFT implementation tools.
• Familiarity with JTAG, IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT concepts.
• Experience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies.
• Experience analyzing DFT readiness, lint, controllability, observability, and test coverage issues.
• Understanding of MBIST planning, implementation, verification, and debug.
• Understanding of low-power design concepts such as power gating, multi-voltage domains, multi-Vt usage, isolation, retention, and voltage scaling.
• Understanding of high-performance and low-power digital design fundamentals.
• Knowledge of common fault models, including stuck-at, transition, path delay, gate-exhaustive, IDDQ, and cell-aware fault models.
• Demonstrated ability to investigate and resolve issues across RTL, gate-level netlists, constraints, patterns, and silicon behavior.
• Ability to communicate technical information effectively and collaborate across design, verification, CAD, physical design, and test engineering teams.
• Candidates are encouraged to apply even if their experience does not include every tool or technology listed above. Experience with comparable tools, methodologies, and technically relevant environments may also be considered.

ACADEMIC CREDENTIALS:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant technical education and industry experience where appropriate.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.