Sr. STAFF/STAFF SILICON DESIGN ENGINEER (PCIe)

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Sr. STAFF/STAFF SILICON DESIGN ENGINEER (PCIe)

THE ROLE:

AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of verifying a leading edge PCIe Controller Sub-System Design. In this role you will be given an opportunity to work on the next generation Power optimization technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for the Verification of several critical blocks, interoperability of lower level IPs and the SubSystem delivery to SoC. The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.

LOCATION:

• Primary - Cork
• Secondary - Dublin

THE PERSON:

A successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.

KEY RESPONSIBILITIES:

• Work on PCIe Controller verification execution from test plan to verification signoff.
• Collaborate with architects and designers to understand the IP features.
• Write/Implement/Review Test Plans.
• Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.
• Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability.
• Build testbench components and develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.
• Conduct and participate in Code Reviews.
• Technical leadership, including block ownership from start to finish and verification sign-off.

PREFERRED EXPERIENCE:

• Experience with Low Power verification techniques and UPF flow is highly desirable
• PC System Architecture: PCI Express, SATA, USB, Ethernet, HyperTransport, DDR. Excellent knowledge of standard bus/interface protocols (i.e., AXI, AHB, AMBA, OCP, PIPE).
• Exposure to AI implementation to improve verification flows
• Experience with simulation profiling, efficiency improvements, acceleration, HLS tools/process.
• Must be a self-starter, and able to drive independently and efficiently challenge time-critical tasks to on-time completion.
• Strong communication, time management, and presentation skills.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Proven experience in verifying commercially successful IPs, Subsystems and or SoCs.
• Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical skills and provide a positive influence on team morale and culture.
• Must be expert in SystemVerilog, UVM.
• Proficient in object-oriented programming, scripting (Ruby, Python, Perl), and low-level programming languages.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Electronics/Computer/Electrical Engineering with 7+ years of relevant DV experience

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

Sr. STAFF/STAFF SILICON DESIGN ENGINEER (PCIe)

THE ROLE:

AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of verifying a leading edge PCIe Controller Sub-System Design. In this role you will be given an opportunity to work on the next generation Power optimization technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for the Verification of several critical blocks, interoperability of lower level IPs and the SubSystem delivery to SoC. The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.

LOCATION:

• Primary - Cork
• Secondary - Dublin

THE PERSON:

A successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.

KEY RESPONSIBILITIES:

• Work on PCIe Controller verification execution from test plan to verification signoff.
• Collaborate with architects and designers to understand the IP features.
• Write/Implement/Review Test Plans.
• Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.
• Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability.
• Build testbench components and develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.
• Conduct and participate in Code Reviews.
• Technical leadership, including block ownership from start to finish and verification sign-off.

PREFERRED EXPERIENCE:

• Experience with Low Power verification techniques and UPF flow is highly desirable
• PC System Architecture: PCI Express, SATA, USB, Ethernet, HyperTransport, DDR. Excellent knowledge of standard bus/interface protocols (i.e., AXI, AHB, AMBA, OCP, PIPE).
• Exposure to AI implementation to improve verification flows
• Experience with simulation profiling, efficiency improvements, acceleration, HLS tools/process.
• Must be a self-starter, and able to drive independently and efficiently challenge time-critical tasks to on-time completion.
• Strong communication, time management, and presentation skills.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Proven experience in verifying commercially successful IPs, Subsystems and or SoCs.
• Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical skills and provide a positive influence on team morale and culture.
• Must be expert in SystemVerilog, UVM.
• Proficient in object-oriented programming, scripting (Ruby, Python, Perl), and low-level programming languages.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Electronics/Computer/Electrical Engineering with 7+ years of relevant DV experience

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.